Analysis and design of low-energy flip-flops

Marković, Dejan; Nikolić, Borivoje; Brodersen, R.W.

doi:10.1109/lpe.2001.945371

Cited by 89 publications

(57 citation statements)

References 9 publications

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“…The Write-Port Master Slave Flip flop (WPMS FF) [8], [9] is shown in Figure.4. It is similar to the FF analyzed in the previous section (TGMS FF) but replaces transmission gates with Pass Transistors (PT) to reduce the clock load, employs partially non-gated keepers and introduces additional logic to speed up the operation of the keepers that have to recover the threshold loss due to pass transistors.…”

Section: B Write-port Master-slave Ffmentioning

confidence: 99%

A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure Design

R.Murugasami¹

2013

IOSR-JECE

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Section: B Write-port Master-slave Ffmentioning

confidence: 99%

A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure Design

R.Murugasami¹

2013

IOSR-JECE

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“…Another performance metric used in other works [14] consists in evaluating the sum (2) where is the nominal delay and is defined as data to clock offset that corresponds to a relative increase by in the delay from its nominal value. The selection of the value of is somewhat arbitrary.…”

Section: A Performance Measurementmentioning

confidence: 99%

“…A number of papers have proposed new styles of latches and flip-flops that improve speed [8], [9], [13], [18], [19], [27], reduce energy [7], [14], [16], [17], [30], or demonstrate improvements in other important characteristics of timing elements, such as race immunity, noise immunity, and testability [12], [14]. Other works have compared various latch styles in the energy-performance design space and established a robust methodology for the comparison [6], [12], [15], [23], [24], [29].…”

mentioning

confidence: 99%

Optimization of scannable latches for low energy

Zyuban

2003

IEEE Trans. VLSI Syst.

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Abstract-This paper covers a range of issues in the design of latches and flip-flops for low-power applications. First it revisits, extends, and improves the energy-performance optimization methodology, attempting to make it more formal and comprehensive. The data-switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of an energy-efficient family of configurations is introduced to make the comparison of different latch styles in the energy-performance space more fair. A recently proposed methodology for balancing hardware intensity in processor pipelines is applied to latch design to facilitate the selection of the objective function for tuning transistor sizes. The power dissipation of the clock distribution is taken into account, supported by simulations of extracted netlists for multibit datapath registers. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power level-sensitive scan mechanism is proposed, and results of a comparative study of scannable latches are shown. The applicability of the proposed scan mechanism to a wide variety of latches is demonstrated.

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“…The internal race immunity is a figure of merit to characterize the robustness of a FF against race conditions and is defined as the difference between clock-to-Q delay and hold time. Hence, the race immunity strongly depends on the specific FF type [2].…”

Section: Introductionmentioning

confidence: 99%

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

Neuberger¹,

Wirth²,

Kastensmidt³

et al. 2009

VLSI-SoC: Advanced Topics on Systems on a Chip

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Abstract. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we investigate the variability of flip-flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ~1ps is used to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to-die variations of hold time violations are measured in various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12-16%. Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm. Normality tests to check if the variability follows a normal Gaussian distribution are also presented.

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Analysis and design of low-energy flip-flops

Cited by 89 publications

References 9 publications

A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure Design

A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure Design

Optimization of scannable latches for low energy

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

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