A 2.4 GHz low power CMOS transceiver for LR-WPAN applications

Liu, Weiyang; Chen, Jingjing; Liu, Xiaodong; Wu, Nanjian

doi:10.1007/s11432-013-4981-8

Cited by 4 publications

(3 citation statements)

References 18 publications

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“…One of the solutions is to reduce the channel length of the device so that the structure of the MOSFET is not totally changed but the device performances are improved. The nowadays technology, MOSFET is the dominant device used in VLSI and ULSI circuits [1][2][3][4][5] because it can be scaled down to nono dimensions than other types of transistors. As a result of the great development in the techniques required to manufacture devices with dimensions below a micron, there appeared technical limitations related to the basic limits of the dimensions of the device based on physical laws.…”

Section: Introductionmentioning

confidence: 99%

Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

Abdul-kadir¹,

Mohammad²,

Hashim³

2020

TELKOMNIKA

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The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET's designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.

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Section: Introductionmentioning

confidence: 99%

Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

Abdul-kadir¹,

Mohammad²,

Hashim³

2020

TELKOMNIKA

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“…A phase-locked loop (PLL) is the critical building block in many integrated circuits such as high-speed analog-to-digital converters (ADC), transceivers, and system-on-chip (SOC) circuits. [1][2][3][4][5] The PLL has several key performance specifications such as low jitter, low power consumption, and robustness to environmental interference.…”

Section: Introductionmentioning

confidence: 99%

2.4–3.2 GHz robust self-injecting injection-locked phase-locked loop

Yang¹,

Zhang²,

Qi³

et al. 2018

Jpn. J. Appl. Phys.

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In this paper, we propose a robust self-injecting injection-locked phase-locked loop (SI-ILPLL). It adopts a phase alignment loop (PAL) based on a subsampling phase frequency detector to align the phase between the injected pulse and the voltage-controlled oscillator (VCO) output. With the proposed phase frequency detector, the PAL performs phase alignment and the pulse generator can self-inject pulses into the VCO for injection locking. The subsampling phase detection and self-injection locking techniques can suppress the phase noise of the SI-ILPLL. The SI-ILPLL shows excellent robustness to environmental interference. The SI-ILPLL is implemented in 65 nm CMOS technology. It occupies an active area of 0.7 mm 2 . The measured root-mean-square (RMS) jitters at 3.2 GHz output without and with injection locking are 216 and 131 fs, respectively. When the supply voltage varies from 1.17 to 1.23 V and the temperature varies from 0 to 80 °C, the maximum jitter variation of all the output frequencies is less than 50 fs. The measured results demonstrate that even when a large interference appears at the supply voltage and unlocks the SI-ILPLL, the SI-ILPLL can self-recover its injection-locked state rapidly after the disturbance disappears, whereas the conventional ILPLL cannot self-recover its locked state after losing it. The power consumption of the SI-ILPLL is 7.4 mW under a 1.2 V supply voltage. The SI-ILPLL achieves a figure of merit (FOM) of %249 dB.

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“…Depending on the applications, the topologies of transceiver ICs or systems may vary considerably in terms of the system architecture and performances such as data-rate, power consumption, physical dimensions, etc. [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 ]. For example, Complementary Metal Oxide Semiconductor (CMOS) RF transceivers for short-range communications have been reported extensively, but it is still of a great importance to design transceivers for certain applications since no one solution can cover all the desires in different scenarios where the design strategies may vary significantly.…”

Section: Introductionmentioning

confidence: 99%

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks

Hou

Chen

Wang

et al. 2017

Sensors

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In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm2 (1.2 mm2 including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of −60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

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A 2.4 GHz low power CMOS transceiver for LR-WPAN applications

Cited by 4 publications

References 18 publications

Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

2.4–3.2 GHz robust self-injecting injection-locked phase-locked loop

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks

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