A 20 mA quiescent current 40% PAE WCDMA HBT power amplifier module with reduced current consumption under backoff power operation

Hau, Gary; Caron, Simon; Turpel, J.; Macdonald, Brian

doi:10.1109/rfic.2005.1489645

Cited by 17 publications

(9 citation statements)

References 5 publications

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“…In previously proposed methods for RF transistor array reconfiguration (e.g., [9]- [12]), external digital control lines are used to minimize current consumption by reconfiguring the PA to reduce quiescent current, or completely shutoff arrays, as the average transmitted power level is lowered. Drawbacks of these methods include: 1) increased number of external control lines as the number of hardware states increases; 2) synchronization of state activation from outside the PA; and 3) demanding temperature-dependant gain calibration requirements, since a typical-behavior lookup table of gain correction factors may not be sufficient to compensate for large and nonlinear gain perturbations that occur upon hardware reconfiguration.…”

Section: State-of-the-art and The Proposed Methodsmentioning

confidence: 99%

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Automatic Hardware Reconfiguration for Current Reduction at Low Power in RFIC PAs

Constantin

Zampardi

El-Gamal

2011

IEEE Trans. Microwave Theory Techn.

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Abstract-This paper presents a novel hardware reconfiguration technique implemented in a dual integrated-circuit (IC) GaAs HBT power amplifier (PA) design and demonstrates reduced current and improved efficiency at low power. The method automatically reconfigures the hardware of an RF IC PA over a given power transmission. Hardware interfacing and synchronization from outside the PA is minimized, and automatic gain compensation upon hardware reconfiguration is achieved with minimal temperaturedependant calibration. The challenge of integrating such complex on-chip hardware functions in a GaAs HBT technology was circumvented by the introduction of a gating concept used in conjunction with envelope feedback, and careful tradeoffs between circuit complexity and performance. Designs that suit the on-chip integration of the technique in GaAs HBT or Si bipolar junction transistor technologies are described. Experimental data are reported to support the proposed method.

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Section: State-of-the-art and The Proposed Methodsmentioning

confidence: 99%

“…[9]- [12]). Such large current reductions show the importance of circuit techniques for RF transistor switching in RFIC PAs.…”

mentioning

confidence: 99%

Automatic Hardware Reconfiguration for Current Reduction at Low Power in RFIC PAs

Constantin

Zampardi

El-Gamal

2011

IEEE Trans. Microwave Theory Techn.

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“…Therefore, further improvements of the PA efficiency at the low average power levels are desired to extend the battery lifetime of mobile devices. Besides using the dynamic power-supply tracking/modulation techniques, several methods have been reported to reduce the PA current consumption at the low power mode, such as device size switching [17]- [20], [23], parallel amplification [21]- [23], switchable power combiner [24], Doherty PA [9], etc. In the recent literature, combinations of different techniques have also been reported.…”

Section: Introductionmentioning

confidence: 99%

“…Using different sizes of power cells for the low power and high power modes of the PA is a simple solution with low cost for the enhancement of low-power efficiency [17]- [20]. In this work, we will adopt the combination of the ET and transistor resizing techniques to a cascode SiGe PA [27], [31], as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

Lopez

Schecht

et al. 2012

IEEE J. Solid-State Circuits

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This paper presents the design insights for the implementation of a fully monolithic radio frequency (RF) power amplifier (PA) using both envelope-tracking (ET) and transistor resizing techniques for long-term evolution (LTE) applications. At the low output power region, some of the power cells in the PA can be disabled to further save power consumption, thus enhancing the efficiency from a traditional ET-PA. Our ET-PA system is first realized with a two-chip solution, consisting of a high voltage envelope modulator fabricated in a 0.35 m Bipolar-CMOS-DMOS (BCD) technology, and a differential cascode PA in a 0.35 m SiGe BiCMOS technology. This two-chip solution of the ET-PA is to showcase the effective efficiency enhancement of using the transistor resizing method. In the second design, a CMOS envelope modulator is integrated with the cascode PA on the same die in the 0.35 m SiGe BiCMOS technology. Some insights are demonstrated regarding the optimization of the envelope modulator specific to our cascode PA for LTE broadband signals, where the finite bandwidth and the switching frequency of the envelope modulator are considered for achieving the minimal error-vector magnitude (EVM) and spurious noise. The fully monolithic BiCMOS ET-PA reaches the maximum linear output power ( ) of 24 dBm and 23.4 dBm with overall power-added-efficiency (PAE) of 41% and 38% for the LTE 16QAM 5 MHz and 10 MHz signals at 1.9 GHz, respectively, without needing predistortion. At the low power mode of our ET-PA, an additional PAE enhancement of 4% is obtained at of 16-20 dBm by disabling some of the PA power cells. Our fully monolithic ET-PA satisfies the LTE 16QAM linearity specs with high efficiency. Index Terms-Bipolar-CMOS-DMOS (BCD), cascode power amplifier (PA), envelope modulator, envelope-tracking (ET), long-term evolution (LTE), low power mode, SiGe BiCMOS, transistor resizing.

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“…Most commercial WCDMA/LTE power amplifiers use a two-stage class AB biased GaAs HBT amplifier to achieve linearity and maximum PAE at higher power levels [1]- [3]. However, there continues to be significant effort aimed at reducing the cost and size of these PAMs while maintaining or even increasing performance levels and functionality.…”

Section: Introductionmentioning

confidence: 99%

A WCDMA 41% power efficiency direct DC coupled hybrid CMOS/GaAs power amplifier with pre-distortion linearization

Leipold¹,

Allen²,

Sheehy³

et al. 2012

2012 IEEE Radio Frequency Integrated Circuits Symposium

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A 1710-1755MHz hybrid power amplifier module (PAM) consisting of a CMOS driver and a GaAs HBT output stage is described. By using multiple parallel CMOS driver stages the gain and bias current expansion needed to maintain the linearity into class C operation of the bipolar output stage is generated. This extends the linear output power range by 0.5 dBm and increases the power added efficiency (PAE) at ACLR1 of -40dBc from 39.0% at 28 dBm output power to 41.3% at 28.5 dBm output power for a WCDMA modulated signal. The PA achieves 43.5% PAE at 29 dBm Pout for an ACLR1 of -37 dBc with a gain of 26 dB and supply voltage of 3.4V.

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A 20 mA quiescent current 40% PAE WCDMA HBT power amplifier module with reduced current consumption under backoff power operation

Cited by 17 publications

References 5 publications

Automatic Hardware Reconfiguration for Current Reduction at Low Power in RFIC PAs

Automatic Hardware Reconfiguration for Current Reduction at Low Power in RFIC PAs

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

A WCDMA 41% power efficiency direct DC coupled hybrid CMOS/GaAs power amplifier with pre-distortion linearization

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