A 205/275GHz fT/fmax Airgap Isolated 0.13 m BiCMOS Technology featuring on-chip High Quality Passives

Huylenbroeck, Stefaan Van; Choi, L.J.; Sibaja-Hernandez, A.; Piontek, A.; Linten, Dimitri; Dehan, M.; Dupuis, O.; Carchon, G.; Vleugels, F.; Kunnen, E.; Leray, Philippe; Devriendt, K.; Shi, Xiaoping; Loo, Roger; Hijzen, E.A.; Decoutere, Stefaan

doi:10.1109/bipol.2006.311158

Cited by 9 publications

(4 citation statements)

References 4 publications

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“…The high drain currents were achieved by inserting the P gate doping step before low thermal budget process of SiGe HBT formation. This process differs from other BiCMOS processes [15], [17], [18], [23]- [30], [35] as described in detail in Section III. A reported SiGe HBT has an f T of 140 GHz, a maximum oscillation frequency (f MAX ) of 183 GHz, and a BVceo of 1.9 V [19], [21].…”

Section: Basic Concept Of Constructing Bicmos Processmentioning

confidence: 99%

“…Several SiGe HBTs have been developed using a combination of blanket SiGe epitaxial growth to form the intrinsic base region and selective boron-doped Si epitaxial growth to form the elevated extrinsic base layer [23], [30], [35]. The intrinsic base region of Hitachi's SiGe HBT is formed using selective SiGe epitaxial growth inside an emitter hole (Fig.…”

Section: A Optimize Order Of Thermal Processing Stepsmentioning

confidence: 99%

“…The use of a 1.0 μm wide trench with an air gap was reported to result in a record peripheral substrate capacitance of 0.02 fF/μm [35]. While a wider trench can suppress parasitic substrate capacitance, thicker oxide deposition is needed to fill a wider deep trench.…”

Section: B Perform Global Planarizationmentioning

confidence: 99%

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A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

Hashimoto

Nonaka

Tominari

et al. 2013

IEEE J. Electron Devices Soc.

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Hitachi's SiGe BiCMOS technology, which integrates 0.18 μm CMOS and a SiGe heterojunction bipolar transistor (HBT), does not degrade MOS or bipolar performance. The BiCMOS process is divided into blocks, and the ordering of their processing is optimized so that they do not interfere with each other. Low-thermal-budget SiGe HBT formation is achieved using a minimal-moisture-desorption oxide layer, thereby avoiding disturbing the CMOS process. This technology, which can also be applied to the 0.13 μm generation, has been used for applications ranging from high-speed ones like automotive radar and 40 Gbps optical communication to consumer ones like wireless.

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Section: Basic Concept Of Constructing Bicmos Processmentioning

confidence: 99%

Section: A Optimize Order Of Thermal Processing Stepsmentioning

confidence: 99%

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A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

Hashimoto

Nonaka

Tominari

et al. 2013

IEEE J. Electron Devices Soc.

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“…Lateral and vertical scaling of the bipolar device dimensions is an absolute requirement for obtaining high operating frequencies (f T , f max ) above 200GHz (1)(2)(3). With the constant aggressive scaling of lateral and vertical transistors dimensions, 2D and 3D effects become more dominant and the difficulty of obtaining reliable process simulations increases.…”

Section: Introductionmentioning

confidence: 99%

2D-TCAD Process Calibration for a High Speed QSA SiGe:C HBT Verified with SSRM

Sibaja-Hernandez¹,

Eyben²,

Huylenbroeck³

et al. 2006

ECS Trans.

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In this work, a 2D-TCAD process simulation platform for high speed bipolar HBT devices with ƒT/ƒmax values exceeding 200GHz is presented. The process simulations implement a consistent model describing the diffusion behavior of boron and carbon in silicon and silicon germanium. In particular, the model successfully accounts for coupled diffusion of carbon and silicon point defects under several RTA conditions. The Kick-Out and Frank-Turnbull reactions model the carbon diffusion. Extended short-loop experiments under equilibrium and non-equilibrium conditions increased the accuracy of the simulations. It is shown that 2D-TCAD process simulations, calibrated with SIMS and TEM pictures, can be successfully complemented with the use of SSRM measurements, which provide emitter-base and collector- base junction delineation and two-dimensional carrier distributions. An excellent agreement in vertical and lateral electrical junction depths between SSRM measurements and the 2D-TCAD simulations validates the 2D process calibration.

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Collector-substrate modeling of SiGe HBTs up to THz range

Saha

Fregonèse

Panda

et al. 2019

2019 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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A 205/275GHz fT/fmax Airgap Isolated 0.13 m BiCMOS Technology featuring on-chip High Quality Passives

Abstract: A QSA airgap isolated HBT module, embedded in a 0.13µm BiCMOS technology, reaches f T /f max values of 205/275GHz and a 3.5ps CML gatedelay. A 17GHz LNA using high quality passives sustains above 8kV HBM ESD stress.

Cited by 9 publications

References 4 publications

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

A Flexible 0.18 $\mu{\rm m}$ BiCMOS Technology Suitable for Various Applications

2D-TCAD Process Calibration for a High Speed QSA SiGe:C HBT Verified with SSRM

Collector-substrate modeling of SiGe HBTs up to THz range

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