A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

Sharma, Vishal; Gopal, Maisagalla; Singh, Pooran; Vishvakarma, Santosh Kumar

doi:10.1016/j.aeue.2018.01.030

Cited by 29 publications

(6 citation statements)

References 22 publications

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“…The dynamic read noise margin (DRNM) of the SRAM cell is defined as a minimum difference between the storage nodes (Q and QB) to be measured during the transient response of the read operation condition [30]. Figure 9a shows the transient response of the DRNM for the conventional 6T and proposed D 2 LP10T cells with a value of 381 and 396 mV, respectively.…”

Section: Dynamic Read Noise Marginmentioning

confidence: 99%

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

et al. 2021

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This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

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Section: Dynamic Read Noise Marginmentioning

confidence: 99%

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

et al. 2021

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“…This technique also introduces area overhead. Read decoupled partial feedback cutting 9T subthreshold SRAM cells (RDPFC 9T) [26] have been presented using the 65 nm technology node to lower the leakage power and achieve higher read stability than CMOS 6T SRAM cells. This design approach, however, has an area overhead of 1.45 times that of the 6T SRAM cell.…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

Tripathi¹,

Chauhan

Singh³

2018

JLPEA

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The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology.

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“…Hence, the write-ability and read stability can be optimized independently, which facilitates a low-voltage operation [9]. Several SRAM designs with decoupled read port have been proposed to overcome the limitations in conventional 6 T SRAM [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24]. Although read upset issue and reduced I ON /I OFF ratio issue have been subdued significantly, most of the cells still suffer from varying data-dependent leakage.…”

Section: Introductionmentioning

confidence: 99%

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Sharif¹,

Ahmad²,

Alam³

2022

Semicond. Sci. Technol.

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Read decoupled SRAM cells were proposed to address the conflicting Read and Write requirements in conventional 6T SRAM cells. However, even read decoupled SRAM cells face several challenges like degraded cell stability, data dependent read bitline (RBL) leakage, deteriorated RBL swing which causes the failure in read sensing at scaled voltages. Therefore, in this work, we propose a read decoupled 9T SRAM cell which improves the read performance. The proposed cell utilizes decoupled read port that significantly improves the read delay, ION/IOFF ratio, bitline leakage as compared to the existing read decoupled cells. The proposed read buffer, having only one transistor in the read path, offers much lower read delay as compared to the existing read buffers. The RBL leakage in the proposed design is also data independent, which significantly improves the RBL sensing margin. We analyse and compare the proposed SRAM cell with existing cells using HSPICE simulations with 16nm FinFET PTM technology. We observe that at a voltage of VDD = 0.35V, the proposed SRAM cell offers ~55% smaller read delay with only 8% increase in leakage power as compared to conventional 6T cell. However, the proposed SRAM cell incurs smallest leakage penalty and offers fastest read operation than the existing read buffer based SRAM cells. Attributed to the negligible bitline leakage in the proposed cell, it offers the highest RBL sensing voltage attributed to closeness of RBL voltage for read ‘1’ to VDD as compared with the other cells. Monte Carlo simulations are also carried out to confirm the robustness of the proposed design under PVT variations. We observe that the proposed SRAM cell is robust and supports voltage scaling and hence could be an attractive choice for low voltage and low power applications.

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A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

Cited by 29 publications

References 22 publications

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

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A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

Cited by 29 publications

References 22 publications

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

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A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications