A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

Abstract

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products. IntroductionAs CMOS technology scales down to 22nm, traditional planar transistor architectures [1-3] have reached a fundamental limit for the required short channel control necessary to continue scaling at the rate dictated by Moore's Law. Recently, novel 3-D Tri-Gate transistors have been proven to be capable of high volume manufacturing for high performance CPU products [4]. This paper reports, for the first time, a leading edge 22nm SoC process technology featuring 3-D Tri-Gate transistors which employs high speed logic transistors, low standby power transistors and highvoltage tolerant transistors simultaneously in a single SoC chip to support a wide range of products, including premium smart phones, tablets, netbooks, embedded systems, wireless communications, and ASIC products.

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

“…The end of the planar device era was marked with the introduction in 2011 of the 22-nm Tri-Gate device. 1,2 Figure 1 shows its design with gates surrounding the channel on three sides of vertical fins to improve gate delay.…”

Advanced system on a chip design based on controllable-polarity FETs

“…3). The combined effect in the decoder design corresponds to {26.66µm 2 , 0.29ns, 9.57mW} (Fig. 9Compact Gates).…”

“…The initial performance of such SoC platform are coarsegrain estimated for a CMOS 22-nm technology node, scaling original data from [19], using tri-gate FinFETs with LSTP option [2]. We employ the techniques presented so far to design an optimized Polar code decoder using TIG controllable-polarity SiNWFET technology.…”

“…Note that DIG behavior can be derived from the conditions where PG S =PG D . The level of performances, i.e., the oncurrent level or the leakage floor are similar to a FinFET Low STandby Power (LSTP) technology [2]. In the following, comparisons will always be carried out with regards to LSTP technology.…”

“…At the advanced 22-nm technology node, FinFET transistors provide an alternative to planar devices in order to build higher-performance low-power SoCs [1,2]. To push device performances even further, vertically-stacked Silicon NanoWire FETs (SiNWFETs) with gate-all-around control are considered the natural extension of FinFETs [3].…”