A 256 × 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator

Burns, D. C.; Underwood, Ian; Gourlay, J.; O’Hara, A.; Vass, D.G.

doi:10.1016/0030-4018(95)00414-4

Cited by 31 publications

(5 citation statements)

References 5 publications

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“…2. The 256 SRAM device (256 2 pixels) fabricated by AMS using a 1.2-µm 5.5V n-well, double metal CMOS process [2], developed and manufactured in 1995.…”

Section: Resultsmentioning

confidence: 99%

26.3: Investigation of the Bow of Silicon Backplanes for Microdisplay Applications

Bodammer¹,

Calton²,

Underwood

2001

Symp Digest of Tech Papers

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“…2. The 256 SRAM device (256 2 pixels) fabricated by AMS using a 1.2-µm 5.5V n-well, double metal CMOS process [2], developed and manufactured in 1995.…”

Section: Resultsmentioning

confidence: 99%

26.3: Investigation of the Bow of Silicon Backplanes for Microdisplay Applications

Bodammer¹,

Calton²,

Underwood

2001

Symp Digest of Tech Papers

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“…Backplane Chip bow causes distortion of a reflected wavefront and large scale variations in FLC thickness and alignment, again resulting in noticeable contrast variations (manifesting as colour fringes in a microdisplay) [3].…”

Section: Key Technologiesmentioning

confidence: 99%

<title>Review of the history and technology of micromachined miniature displays using foundry-produced silicon backplanes</title>

et al. 1999

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“…As this latter technology matured, it led to the production of the first commercially available picture-quality colour active-matrix (AM) P-OLED display [14]. Similarly, Liquid Crystal on Silicon (LCoS) microdisplay technology was developed using foundry CMOS postprocessed with extra metal layers, planarisation and spacers for liquid crystal integration and packaging [15]- [18]. This process has also become a foundry offering [19].…”

Section: Introductionmentioning

confidence: 99%

Comparison of Conventional and Maskless Lithographic Techniques for More than Moore Post-Processing of Foundry CMOS Chips

Tsiamis

Dunare

et al. 2020

J. Microelectromech. Syst.

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This paper details and compares the technology options for post-processing foundry produced CMOS at chipscale to enable More than Moore functionality. In many cases there are attractions in using chip-based processing through the Multi-Project Wafer route that is frequently employed in research, early-stage development and low-volume production. This paper identifies that spray-based photoresist deposition combined with optical maskless lithography demonstrates sufficient performance combined with low cost and operational convenience to offer an attractive alternative to conventional optical lithography, where spin-coated photoresist is exposed through a patterned photomask.

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A 256 × 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator

Cited by 31 publications

References 5 publications

26.3: Investigation of the Bow of Silicon Backplanes for Microdisplay Applications

26.3: Investigation of the Bow of Silicon Backplanes for Microdisplay Applications

<title>Review of the history and technology of micromachined miniature displays using foundry-produced silicon backplanes</title>

Comparison of Conventional and Maskless Lithographic Techniques for More than Moore Post-Processing of Foundry CMOS Chips

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