A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit

Abstract

A low power 10-bit 125-MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) based on MOS bucket-brigade devices (BBDs) is presented. A PVT insensitive boosted charge transfer (BCT) that is able to reject the charge error induced by PVT variations is proposed. With the proposed BCT, the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably. The prototype ADC based on the proposed BCT is realized in a 0.18 m CMOS process, with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm 2 . The prototype ADC achieves a spurious free dynamic range (SFDR) of 67.7 dB, a signal-to-noise ratio (SNDR) of 57.3 dB, and an effective number of bits (ENOB) of 9.0 for a 3.79 MHz input at full sampling rate. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are C0:5/ 0:3 LSB and C0:7/ 0:55 LSB, respectively.

A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit

“…The replica circuit is in the bottom part of the ADC. Excluding the die area occupied by PAD and ESD cells, the total active area of the CD pipelined ADC is about 1.2 1.3 mm 2 , where the die area of the S&H and tapered CD pipeline stages is the same as that in Reference [4]. Compared with the 10-bit CD pipeline ADC report in Reference [4], the replica circuit used in this paper increased the die area of 0.4 1.2 mm 2 .…”

“…Figure 6 shows the block construction of the 10-bit 250 MSPS BBD based CD pipelined ADC, which is the same structure as the CD pipeline ADC reported in Reference [4]. The difference is that the BCTs used in this ADC are replaced by the replica controlled BCTs.…”

“…The high-speed CD pipeline ADC report in References [3,4] adopts a differential difference amplifier (DDA) to control the cut-off voltage of the BCT circuits to eliminate the CM charge error accumulation. However, because the DDA is used to compare the difference between the drain and the source voltages of the charge transfer switch with a differential reference voltage dynamically, the termination of the charge transfer process becomes more complex for the BCT circuit with DDA.…”

A 12-bit 250-MS/s charge-domain pipelined analog-to-digital converter with feed-forward common-mode charge control

“…The PVT insensitive BCT circuit reported in Refs. [11][12][13][14] can be used to accurately control the variation in CM charge caused by the variation in Q c in the SH circuit and the N 1 CD pipelined sub-stages. Q icm is determined by the analog input CM voltage and the sampling capacitors.…”

“…The pseudo-differential-assisted and replica-controlled PVT insensitive BCT circuit reported in Refs. [11][12][13][14] effectively calibrates the CM charge deviations caused by PVT variations. However, these BCT circuits only control the CM charge errors introduced during the charge transfer process; the input CM charge error from outside the ADC cannot be either processed or controlled.…”