A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

Abstract

TXNonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy [1] and high-performance systems managing power by operating "normally off" [2]. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data. This chip's process technology features embedded ferroelectric capacitors that store data in a charge versus bias voltage hysteresis [3]. This hysteresis is shown in Fig. 1 along with the principle of self-timed sensing. Prior to sensing, the fecaps have been programmed to opposite data states, corresponding to opposite points on the zero bias voltage points of the hysteresis curve. Identical charging currents integrate the difference in remnant charge between the two fecaps onto nodes FET and FEC. The node to first cross the diode voltage drop plus a PMOS threshold will quickly pull the internal node of the sensing latch high. The ferroelectric capacitance is large compared to the internal node of the sensing latch, so a small voltage difference on the high capacitance nodes FET and FEC is converted to a large voltage difference on the latch nodes. In addition to being self-timed, this approach develops sufficient bias (1.1 V) before the fecaps are sensed. Fecap signal dynamics are exponentially sensitive to voltage bias [4], so it is important to avoid the performance penalty associated with sensing at low bias.The schematic of the nonvolatile latch in Fig. 2 shows the additional transistors for saving data, isolating fecaps during active operation, and protecting fecaps during power loss. This latch is combined as the slave stage with a clocked CMOS master latch to form the NVDFF in Fig. 3. The waveforms show how the ports PG, LD, EQ, and VDDNV need to be sequenced during power interruption. While active, PG=LD=0, and nodes FET and FEC act as a virtual supply for the slave latch. The save operation initiates when PG rises as CK is held low, cutting off VDDNV and enabling a weak pull-down path (M8-M10) to discharge one of the two fecaps (write "0") depending on the data state of the slave latch. The subsequent rise of LD preserves the data in the other fecap, which has already been written to a "1" during the previous restore operation. Prior to power loss, the EQ signal assertion clears floating voltages inside the slave latch, and then the VDDNV rail is discharged to prevent conducting paths to nodes FET/FEC. A complementary sequence is applied after VDD and VDDNV return high for ...

Energy-efficient data retention in D flip-flops using STT-MTJ

“…Therefore, emerging non-volatile memory is used to completely eliminate the standby power dissipation. Qazi et al (2013) and Bartling et al (2013) proposed an NVFF using ferroelectric memory (FeRAM). FeRAM is one of the emerging non-volatile memory (NVM) that uses ferroelectric capacitors to store the data.…”

Ambient energy harvesting nonvolatile processors

“…The main concept is to isolate the nonvolatile device from the CMOS flip-flop with switches (M1 and M2), and the nonvolatile devices perform store/recall operations only when power failures happen. [3,4,5,6,7,8]. Table 1 compares their performance of data store and recall.…”

“…Recently, some chips of nonvolatile processors are designed based on different nonvolatile technologies, including FeRAM, STT-MRAM and RRAM [3,4,5,6,7]. The first nonvolatile processor chip, THU-1010N, was based on ROHM's ferroelectric technology [3].…”

“…It achieves 7μs data backup time, 100x faster than the up-to-date commercial microprocessors. After that, researchers in MIT and TI fabricated FeRAM based nonvolatile processors [4,6] and reduced the backup and restore time to hundreds of nanoseconds. Tohoku university and NEC fabricated an STT-MRAM based nonvolatile processor [5], which achieved 4ns backup time and 5ns restore time.…”

SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture

“…Power-gating is a well-known leakage reduction technique where a circuit block is disconnected from its power supply rails during idle (sleep) mode [3]- [6]. In order to perform power-gating without losing the processed data, nonvolatile flip-flops (NVFFs) have been widely investigated [4]- [7]. NVFF acts as a conventional flip-flop during active mode.…”