A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology

Steidl, S.A.; McDonald, J. F.

doi:10.1109/4.982429

Cited by 9 publications

(6 citation statements)

References 7 publications

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“…9 We also explored L1 and L2 implementations. Based on these explorations, we propose a memory architecture suitable for a processor running at 16 GHz.…”

Section: Cache Structurementioning

confidence: 99%

Predicting the Performance of a 3D Processor-Memory Chip Stack

Philip

Erdogan

Zia

et al. 2005

IEEE Des. Test. Comput.

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WE ARE EXPLORING a 3D processor-memory stack for use with the Message Passing Interface (MPI). 1 The communication among processors in huge servers such as the IBM BlueGene/L or the NEC Earth Simulator wastes several thousands of cycles. Most of these wasted cycles do not come from the communication link among the processors across the system, but rather in handling the message packets. A processor that could handle this message packing and communication at a much faster rateon the order of 16 GHz-could significantly increase this task's efficiency and thus increase the utilization of such supercomputers, currently a very low 1%. However, at such high clock rates, the memory wall would become a significant problem. These processor speeds could be achievable in RISC processors using silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS. Processors have been built using BiCMOS technology in the past. 2 The memory architecture would require modification to suit such an application.Tackling this problem requires innovative technologies, such as 3D memories, which alleviate some problems with long on-chip interconnects. The importance of interconnection wires to circuit performance is increasing, because they do not scale like the devices on a chip. The need for shorter interconnection delays suggests shorter interconnection wires. Shorter interconnections are more likely in 3D architectures than in equivalent 2D systems. 3,4 Industry has already carried out several explorative studies in building 3D circuits, including memories and FPGAs (such as the FaStack process, http://www.tezzaron. com). Others have also developed the different waferbonding techniques necessary for 3D integration. The primary advantage of 3D circuits-lower interconnection delay-is also under study in the context of future microprocessors. 5 This article explores the advantages of 3D in a processor-memory stack system. We conducted simulations using simple tools like Dinero IV and the Cache Access and Cycle Time Information (Cacti) to evaluate the performances of various memory architectures.Conventional 2D architectures for processors have the processor and cache in the same plane. L0 and L1 caches are present on the same die as the processor, whereas the L2 cache can be on a separate die. The 2D layout enforces physical constraints on the separation of the processor from the cache. Interconnection wires that connect the processor and cache are long, especially when L2 is in a separate die. This causes multiple clock cycles to pass before data moves from one end to another. Moving to a 3D layout solves some of these problems. The processor we considered is a simple, single-issue RISC processor built using a 7HP SiGe HBT BiCMOS technology featuring minimum bipolar transistor sizes that have a unity gain cut-off frequency (f T ) of 120 GHz. 6

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“…9 We also explored L1 and L2 implementations. Based on these explorations, we propose a memory architecture suitable for a processor running at 16 GHz.…”

Section: Cache Structurementioning

confidence: 99%

Predicting the Performance of a 3D Processor-Memory Chip Stack

Philip

Erdogan

Zia

et al. 2005

IEEE Des. Test. Comput.

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“…Any of the N words can be simultaneously accessed by two read ports and a single write port. The block diagram of the register file that appears in Figure 1 shows that the register file contains seven distinct types of functional blocks (Steidl, 2001). These are the memory cell array, the read address decoders and word line drivers, the write address decoder, the bit line drivers, the sense amplifiers, the output latches and the comparators.…”

Section: Register File Design Overviewmentioning

confidence: 99%

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

Ayala¹,

López‐Vallejo²,

López-Barrio³

et al. 2008

IJES

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This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.Keywords: register file; in-order; power reduction; predecode; hardware approach.

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“…Any of the N words can be simultaneously accessed by any of the ports of the RF (read or write). Figure 1 shows that the RF contains seven distinct types of functional blocks [13]. In this design, the memory cell array stores the data bits, and is arranged in a grid of N rows by M columns of memory cells.…”

Section: A Hw Extensionsmentioning

confidence: 99%

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Raghavan

Ayala

Atienza³

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed variability of the RF proposing different compiletime and run-time design alternatives. The first alternative extends current RF architectures and uses a compile-time variability-aware register assignment algorithm. The second alternative presents a fully-adjustable pure run-time approach, which overcomes the variability loss as well, but at the extra cost of cycles and area. However, the savings achieved and the run-time management of the register delay variations without any support from the user, show a very promising application field. Our results in embedded system benchmarks show that variability can be tackled without significant performance penalty, and trade-offs between performance and area are possible thanks to the whole design spectrum provided by the two presented alternatives. I. INTRODUCTIONNew multimedia consumer applications require high performance embedded platforms due to their intensive processing requirements. In this area of embedded systems, Very Large Instruction Word (VLIW) processors provide a promising solution to achieve suitable performance-power trade-offs. However, transistor scaling in future technology nodes is accompanied by an increase of variability in process technology. Two types of variations exist: functional variation and parametric variation. Functional variation leads to loss in component functionality, while parametric variation leads to timing issues in the working component with respect to its originally designed speed [1], [2], [3].In this paper we present several solutions to handle parametric variation in shared register files of embedded VLIW processors, which provide also trade-offs of precharacterization (design time) effort and dynamic (run-time) overhead for self-tuning. The first solution (Section III) is a hardware/software (HW/SW) approach that relies on limited HW extensions in the Register File (RF), and a modified register assignment phase at compiler level to prevent using marked slow registers. In the latter two approaches (Section IV), we propose further extensions of the RF HW architecture to create completely run-time schemes against dynamic variation in the RF. These run-time approaches do

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A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology

Cited by 9 publications

References 7 publications

Predicting the Performance of a 3D Processor-Memory Chip Stack

Predicting the Performance of a 3D Processor-Memory Chip Stack

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

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