A 3D integration scheme utilizing wireless interconnections for implementing hyper brains

Abstract

In order to break Moore's law by 3D integration, innovative solutions for inter-and intra-chip interconnections have to be developed. Inter-chip interconnection technologies using via-holes have been developed however their associated fabrication cost and yield are still unacceptable. To overcome these problems, wireless interconnects using capacitive coupling of small pads [1] or inductive coupling of on-chip spiral inductors [2] are proposed. With the former technique, since a pair of pads formed on different chips must couple with an insulation layer with the thickness of 1 to 2µm, the problems are not satisfactorily solved. The latter technique consumes large power of more than 10mW for a single interconnect. Therefore, expected requirements of over 1000 connections between chips cannot be realized in practice.Another bottleneck for 3D integration lies in the processing algorithm and architecture of conventional Neumann computers. Although living systems use a vast number of mutually connected neural cells that are sensitive to noise, these systems achieve highly sophisticated capabilities with sufficiently high reliability. To mimic biological systems, a processing architecture for aggregating information and making perspective judgment based on the advanced interconnection techniques is developed.From the view point of a complete system, global interconnects throughout whole chips and local parallel interconnects between adjacent chips are required. The former is used for system clocking over 10GHz as well as busses that enables synchronous processing and accessing to a G-byte database. The latter transfers 2D data such as image data, without the requirement of gathering and multiplexing.The proposed local wireless interconnection scheme (LWI) between chips utilizes the principle of magnetic coupling and resonance of on-chip spiral inductors. A circuit schematic and an inductor structure are shown in Fig. 14.4.1. TX consists of a switching MOST and a pulse shaper, and RX consists of an LC resonator, a detector, and a reconstruction FF. Current and voltage characteristics of the circuit are also shown in Fig. 14.4.1. To optimize transmission delay and power dissipation, the pulse width is set to the time when the inductor current (i L ) reaches its maximum value. FDTD analysis and circuit simulation show found that the inductor size (L ind ) should be larger than twice of the inductor distance (t chip ) to obtain a large enough coupling coefficient (k). These sizes are scalable under a constant current condition.The test chip is developed with a 0.25µm CMOS technology. Two chips are mounted on manipulators for measuring the transfer characteristics. Measured results are also shown in Fig. 14.4.1. A data rate of 800Mb/s is obtained at supply voltage of 2.5V and power consumption of 9mW. By circuit simulation using 0.18µm CMOS devices, 2Gb/s data rate are obtained with only 1mW power dissipation. The LWI can be applied to asynchronous interconnects corresponding to wires as well as synchronous systems using a ...

Wireless Interchip Interconnects

“…The quality factor of the antenna is improved but the bandwidth decreases with decreasing thickness of the Si substrate. The received peak-to-peak voltage does not depend on the number of stacked chips when the resistivity of the Si substrate is 2.29 kΩ cm but it decreases with increasing numbers of chips when the standard Si substrate (10 Ω cm) is used, as shown in Figure 15.15 (c) [31]. The radiation efficiency and the transmission coefficient of the on-chip antenna increase with increasing resistivity and with increasing thickness of the Si substrate, as shown in Figure 15.14.…”

“…A 3D wireless LSI stacked system has been proposed, as shown in Figure 15.5 [30,31]. Local wireless interconnects (LWIs) have been developed between adjacent chips using inductive coupling and capacitive coupling.…”

Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints

“…Wafer-level integration (WLI) can be performed in two ways: entire wafers can be bonded together before dicing (an approach herein after termed 3D-W2W) or KGDs are bonded on top of a host wafer containing other KGD sites, termed (3D-D2W) [17]. Some other possibilities not considered here include capacitive [18], [19] or inductive [20] links for wireless communication between chips [21].…”

Multilayer stacking technology using wafer-to-wafer stacked method

“…3D stacking technology is very promising as a future technology because of its many benefits, such as its high performance, low power, smaller footprint, and enabling of heterogeneous technology integration [RTI 2004[RTI -2007Iwata et al 2005;Topol et al 2005;ISSCC Forum 2007]. Such benefits of the 3D stacking technology will be useful for those computer systems in which there are multiple connection paths between each chip.…”