A 3mW 74dB SNR 2MHz CT ΔΣ ADC with a tracking-ADC-quantizer in 0.13μm CMOS

Dorrer, L.; Kuttner, F.; Greco, P.; Derksen, S.

doi:10.1109/isscc.2005.1494084

Cited by 15 publications

(5 citation statements)

References 6 publications

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“…To increase immunity to interferences, a reconfigurable CT ΣΔ ADC with a feedback loop architecture should be used since its signal transfer function (STF) has a faster roll-off in out-of-channel frequencies in comparison to feedforward loop architectures [14]. The stabilization of the modulator transfer function is performed by using a loopback input at each filter stage [15]. A conventional fourth-order feedback low-pass CT ADCs with a single-bit quantizer is shown in figure 1 [16].…”

Section: The Proposed Reconfigurable Ct σδ Adc Architecturementioning

confidence: 99%

A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

Mallek

Daoud

Aloulou

et al. 2019

IyU

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Objective: In this work the design of a fourth-order Reconfigurable Sigma Delta analog-to-digital converter (ΣΔ ADC) for 5MHz, 7MHz or 10MHz channel bandwidths are presented. Materials and methods: Our design technique aims to keep the same ADC architecture in response to multi-band and multi-mode aspects of Mobile WiMAX standard. To this end, we set each sampling frequency corresponding to each channel bandwidth, in order that the same OSR value would be kept for the different channel bandwidths. This technique is intended to optimize the power and area of the ADC that efficiently covers varying channel bandwidths. Moreover, we use the pole placement method to calculate the optimized filter coefficients of Continuous-Time Sigma-Delta (CT ΣΔ) ADC. Results and discussion: Over 5MHz, 7MHz and 10MHz channel bandwidths, the ADC achieved 72.89dB, 67.26dB and 66.47dB peak SNR values, respectively and a dynamic range of 73.5dB, 69.47dB and 66.5dB respectively with only 28mW, 28.2mW and 28.6mW power consumption respectively. Conclusions: The design of the proposed reconfigurable ADC intended for use in the mobile WiMAX standard were achieved. Moreover, the results obtained are satisfactory and are in accordance with theoretical expectations.

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Section: The Proposed Reconfigurable Ct σδ Adc Architecturementioning

confidence: 99%

A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

Mallek

Daoud

Aloulou

et al. 2019

IyU

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“…A state-of-the-art ∆Σ ADC for W-CDMA has been published in [21], moreover, requirements for uniform bandpass sampling are discussed in [22] with an extensive comparison of maximum jitter error and resolution needs for multi-mode ADCs.…”

Section: B Analog/digital Convertermentioning

confidence: 99%

Multi-Mode Receiver Design for Wireless Terminals

Hueber¹,

Stuhlberger

Holm

et al. 2007

2007 European Conference on Wireless Technologies

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The ongoing evolution from 2G to 3G and beyond confronts the cellular market with the challenges of a broad diversity of communication standards. Furthermore, increasing levels of integration with minimum external component count, advances in semiconductor process technology, and the requirement for multi-mode operation are pivotal demands of the RF-IC manufactures to achieve fast design cycles and low product cost. As a result, reconfiguration of the wireless terminal has become the key issue in the design of wireless terminals. This paper discusses the requirements for multi-mode reconfigurable wireless receivers with focus put onto mixed-signal and digital enhancements to traditional analog front-end designs. The flexibility a digitalfront-end (DFE) introduces is studied with respect to the main cellular communication standards (GSM/EDGE, CDMA2000, W-CDMA/HSDPA, and LTE) and satellite navigation systems (GPS, Galileo), with considerations of impacts on the capability of an implementation of a software-defined-radio (SDR).

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“…Thus, the 3rd-order 4-bit CT ∆Σ-ADC from [9] with the loop-filter modified for CDMA2000 has been implemented. It features 650 kHz loop-filter bandwidth and a measured noise floor of -90 dBFS in the presence of a 900 kHz blocker, which is sufficient for converting the received signal into the digital domain.…”

Section: B Analog/digital Convertermentioning

confidence: 99%

“…The predecessor receive concept is described in [6], a first generation transceiver in [7], the analog-front-end for a CDMA2000 transceiver in [8], the predecessor of the ADC in [9], and the digital interface in [10].…”

Section: Introductionmentioning

confidence: 99%

A Single-chip dual-band CDMA2000 receiver for cellular terminals in 0.13 µm CMOS

Hueber¹

2007

2007 European Microwave Integrated Circuit Conference

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Keeping pace with the steady advances in the development of even finer gate length technologies, CMOS has established as preferred process for radio-frequency design that enables the integration of complex digital circuitry on the same die at reasonable costs in terms of required area and power consumption. A single-chip dual-band CDMA2000 receiver based on zero-IF architecture is presented. In addition to all required analog building blocks for reception in the North-American cellular and PCS bands (Band Class 0 and 1), the chip features a fully integrated synthesizer including VCOs for minimum external component count, analog anti-aliasing filters, a fully configurable digital-front-end (DFE), ∆Σ ADCs, a high-speed digital serial baseband (BB) interface, and a three-wire-bus configuration interface. The DFE's functionality includes samplerate-conversion, channel filtering, dynamic range control, and signal conditioning for data transmission via a digital interface between RFIC and baseband IC. The receiver IC with a die size of 8 mm 2 has been fabricated in 0.13-µm RF-CMOS and shows an error-vector-magnitude (EVM) of 3.1 % and a Rho of 0.998 at the digital baseband interface.978-2-87487-002-6

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A 3mW 74dB SNR 2MHz CT ΔΣ ADC with a tracking-ADC-quantizer in 0.13μm CMOS

Cited by 15 publications

References 6 publications

A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

Multi-Mode Receiver Design for Wireless Terminals

A Single-chip dual-band CDMA2000 receiver for cellular terminals in 0.13 µm CMOS

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A 3mW 74dB SNR 2MHz CT ΔΣ ADC with a tracking-ADC-quantizer in 0.13μm CMOS

Cited by 15 publications

References 6 publications

A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

Multi-Mode Receiver Design for Wireless Terminals

A Single-chip dual-band CDMA2000 receiver for cellular terminals in 0.13 &#x00B5;m CMOS

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A Single-chip dual-band CDMA2000 receiver for cellular terminals in 0.13 µm CMOS