A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

Reutemann, R.; Ruegg, Michael; Keyser, Fran; Bergkvist, John; Dreps, Daniel; Toifl, Thomas; Schmatz, M.

doi:10.1109/isscc.2010.5434008

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Cited by 6 publications

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“…As data and clock jitter is generated by transmitter, the forwarded clock transceivers have better jitter correlation between received data and clock. The receiver and transmitter can be designed and used separately, for less crosstalk between TX and RX [1].…”

Section: Introductionmentioning

confidence: 99%

A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS

Wang

et al. 2012

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This paper describes a 6.4Gb/s data lane circuit in 65nm CMOS process. The data lane circuit consists of an offset cancellation continuous time linear equalizer and a half-rate digital CDR; the CDR bandwidth is programmable by using a digital FIR filter. A common-mode level shift function is implemented in order to use NMOS input CML circuit. The design can compensate over 8 dB channel loss with offsetcalibrated and low noise. The area for one data lane is 0.045 and power consumption is 24.5mW for 1.2V supply.

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Section: Introductionmentioning

confidence: 99%