A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction

Terada, Masaharu; Yoshimoto, Shusuke; Okumura, Satoshi; Suzuki, T.; Miyano, Satoru; Kawaguchi, Hiroshi; Yoshimoto, Masahiko

doi:10.1109/isqed.2012.6187538

Cited by 10 publications

(7 citation statements)

References 10 publications

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“…However, leakage current was a main issue, causing retention fault, particularly for advanced CMOS processes. This issue was not present in the works of Terada et al [14], because they introduced a transistor in their design to act as a leakage bypass. This was at the expense of a larger area overhead.…”

Section: Single-ended Sram Cell Circuit Analysismentioning

confidence: 99%

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A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Wang

Sangalang

Tseng

et al. 2023

IET Circuits, Devices & Syst

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An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and powerdelay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock. K E Y W O R D Sdigital integrated circuits, logic design, low-power electronics, memory architecture, VLSIThis is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Single-ended Sram Cell Circuit Analysismentioning

confidence: 99%

“…This issue was not present in the works of Terada et al. [14], because they introduced a transistor in their design to act as a leakage bypass. This was at the expense of a larger area overhead.…”

Section: Low Energy Sram With Single‐ended Cellsmentioning

confidence: 99%

A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Wang

Sangalang

Tseng

et al. 2023

IET Circuits, Devices & Syst

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“…In the literature, there are several schemes in the device, circuit and system level that have attempted to solve the problems of the halfselected SRAM cells [20][21][22][23][24]. The authors in [20,21] provided a trade-off between the write noise margin and the margin for preserving the data.…”

Section: Previous Half-selection Resilient Schemesmentioning

confidence: 99%

“…In [22], a scheme was proposed to resolve the problems of half‐selected cells, which is not at device or circuit level. The authors in [22] used an 8 T SRAM cell that has two access transistors for the write operation. These access transistors have separate word line signals and can be activated individually.…”

Section: Previous Half‐selection Resilient Schemesmentioning

confidence: 99%

“…By pre‐charging the bitlines to half‐VDD, on average, this voltage difference becomes VDD/2, hence, the immunity of the half‐selected SRAM cell against a current flowing between the cell and the bitlines will increase. In addition, in [22] two word line signals are not activated at the same time. As a result, charges on two bitlines cannot attack the SRAM cell at the same time.…”

Section: Previous Half‐selection Resilient Schemesmentioning

confidence: 99%

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Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

Pasandi

Pedram

2018

IET Circuits, Devices & Systems

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In static random access memory (SRAM), some cells are not selected for writing, but due to the distribution of the word line signals in the SRAM array, their word line signal is activated. Therefore, they may be mistakenly written. Such cells are called half-selected cells. This study presents two schemes, one for single-ended and the other for differential sensing SRAMs, to eliminate the half-selection disturbance. In the first proposed scheme, the content of the desired row of the SRAM array is read before the write operation and is written back on the corresponding write bitlines. This operation results in eliminating the possibility for noise to be written onto the half-selected cells. In the second scheme, a simple read operation is performed before the write operation. The authors applied their half-selection resilient schemes to 8 and 6 T SRAMs. Simulation results show that in the presence of radioactive particles, by applying their write-back scheme to 8 T SRAM and their read-before-write scheme to the conventional 6 T SRAM, the failure rate is reduced from an average of 56 and 20%, respectively, to 0. The proposed schemes do not degrade write-ability of the SRAM cells, and are bit-addressable. Moreover, their proposed schemes consume smaller amounts of power compared with their rivals.

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Design of a stable single sided 11T static random access memory cell with improved critical charge

Sachdeva

2022

Int J Numerical Modelling

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Radiation-induced soft errors are becoming a key challenge in satellite-based communication. The worst-hit component of such devices is static randomaccess memory bit-cells, owing to their high density, large area, and lowoperating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge-boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft-error-immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13Â/1.38Â/0.90Â/1.04Â/1.03Â improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31Â/1.17Â/1.31Â/1.41Â/1.01Â compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97Â/0.98Â/1.91Â/1.24Â/1Â when equated to 6T/PP10T/ AS8T/Quatro10T/LC10T cell. Improved Inter-cell and Intra-cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.

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A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction

Cited by 10 publications

References 10 publications

A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

Design of a stable single sided 11T static random access memory cell with improved critical charge

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