A 400MHz 32b embedded microprocessor core AM34-1 with 4.0GB/s cross-bar bus switch for SoC

Nakajima, M.; Yamamoto, Takashi; Ozaki, Shinji; Sezaki, I.; Kanakogi, Tomochika; FuruzoNo, T.; Sakamoto, Toshiyuki; Aruga, T.; Sumita, M.; Tsutsumi, Masanori; Ueda, A.; Ichinomiya, T.

doi:10.1109/isscc.2002.993072

Cited by 11 publications

(5 citation statements)

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“…Network-on-Chip (NoC) communication architectures [8] have emerged as a promising alternative to handle communication needs for the next generation of highperformance designs, but it fits better with rather larger chips with hundreds of IPs. So we believe that multi-layered bus matrix [22] is currently the most practical way of realizing concurrent communications among tens of modules from the viewpoint of performance and area. Ogawa et al [23] have proposed a transaction-based simulation environment that allows designers to explore and design a bus matrix.…”

Section: On-chip Communication Architecture Designmentioning

confidence: 99%

Communication architecture design for reconfigurable multimedia SoC platform

Lee

Ahn

Lee

et al. 2009

Des Autom Embed Syst

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Memory and communication architecture have a significant impact on the performance, cost, and power of complex multiprocessor system-on-chip designs. In this paper, we present an automated bus matrix synthesis flow for efficient transaction-level design space exploration of communication architecture in a reconfigurable multimedia system-on-chip platform. Specifically, we consider hardware interface selection problem, which has significant effect on the overall cost of area and power. We propose a method to solve such hardware interface selection problem through static analysis of communication behavior. We experiment with JPEG encoder and H.264 encoder examples and the results show the reduction of area by 56.91% and power by 48.61% of bus matrix with 0.58% performance overhead on average compared to the case of maximum performance. According to our HW interface selection algorithm, we also experiment MPEG4 video decoder example. And the result is evaluated on the FPGA prototyping board.

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Section: On-chip Communication Architecture Designmentioning

confidence: 99%

Communication architecture design for reconfigurable multimedia SoC platform

Lee

Ahn

Lee

et al. 2009

Des Autom Embed Syst

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“…Network-on-Chip (NoC)-based communication architectures [20] have recently emerged as a promising alternative to handle communication needs for the next generation of high-performance designs, but research on the topic is still in its infancy, and few concrete implementations of complex NoCs exist to date [21]. Currently, designers are increasingly making use of bus-matrix [18] communication architectures to meet the bandwidth requirements of modern MPSoC systems. The need for bus-matrix architectures in high-performance designs and its superiority over hierarchical shared buses has been emphasized in previous work [22]- [24].…”

Section: Related Workmentioning

confidence: 99%

“…The primary objective is to design a communication architecture having the least number of buses, which satisfies performance and memory-area constraints, while the secondary objective is to reduce the memoryarea cost. We consider a bus-matrix (sometimes also called crossbar switch) [18] type of communication architecture for synthesis, since it is increasingly being used by designers in high-bandwidth designs today.…”

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confidence: 99%

A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC

Pasricha

Dutt

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In this paper we look at bus matrix (sometimes also called crossbar switch) based communication architectures [7] which are currently being considered by designers to meet the high bandwidth requirements of modern MPSoC systems. Fig.…”

Section: Introductionmentioning

confidence: 99%

Constraint-driven bus matrix synthesis for MPSoC

Pasricha

Dutt

Ben-Romdhane

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 × component savings when compared to a full bus matrix and up to 3.2 × savings when compared to a maximally connected reduced bus matrix.

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A 400MHz 32b embedded microprocessor core AM34-1 with 4.0GB/s cross-bar bus switch for SoC

Cited by 11 publications

References 0 publications

Communication architecture design for reconfigurable multimedia SoC platform

Communication architecture design for reconfigurable multimedia SoC platform

A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC

Constraint-driven bus matrix synthesis for MPSoC

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