A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

Garrido, Mario; Sánchez, María del Carmen; López‐Vallejo, Marisa; Grajal, Jesús

doi:10.1109/tvlsi.2016.2567784

Cited by 38 publications

(28 citation statements)

References 13 publications

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“…There are also "memory-based" FFT designs (for reviews see [17,18]) which are usually more flexible and use fewer hardware resources than their pipelined counterpart, although high throughput is difficult to achieve and they are not inherently scalable.…”

Section: Related Workmentioning

confidence: 99%

Distributed-Memory-Based FFT Architecture and FPGA Implementations

Nash¹

2018

Electronics

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A new class of fast Fourier transform (FFT) architecture, based on the use of distributed memories, is proposed for field-programmable gate arrays (FPGAs). Prominent features are high clock speeds, programmability, reduced look-up-table (LUT) and register usage, simplicity of design, and a capability to do both power-of-two and non-power-of-two FFTs. Higher clock speeds are a consequence of new algorithms and a more fine-grained structure compared to traditional pipelined FFTs, so clock speeds are typically >500 MHz in 65 nm FPGA technology. The programmability derives from the memory-based architecture, which is also scalable. Reduced LUT and register usage arises from a unique methodology to control word growth during computation that achieves high dynamic range, along with inherent systolic circuit characteristics: simple, regular, uniform arrays of processing elements, connected in nearest-neighbor fashion to minimize wiring lengths. The circuit goal was to maximize throughput and minimize the use of the FPGA LUT and register logic fabric. Comparison results from seven different designs, covering a spectrum of functionality (fixed-size, variable, floating-point and variable non-power-of-two FFTs), different FPGA vendors (Intel and Xilinx) and different FPGA types, showed increases in throughput per logic cell up to 181% with an average improvement of 94%.

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Section: Related Workmentioning

confidence: 99%

Distributed-Memory-Based FFT Architecture and FPGA Implementations

Nash¹

2018

Electronics

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“…For radar applications, the high throughput of fully parallel FFTs allow for object detection over large bandwidths [17]. Another area of interest of fully parallel FFTs is for applications where iterative FFTs are implemented [18]- [20]. Note that in iterative FFTs [18]- [20], the butterfly of the processing element (PE) usually consists of an r-point fully parallel FFT, where r is the FFT radix.…”

Section: Introductionmentioning

confidence: 99%

“…Another area of interest of fully parallel FFTs is for applications where iterative FFTs are implemented [18]- [20]. Note that in iterative FFTs [18]- [20], the butterfly of the processing element (PE) usually consists of an r-point fully parallel FFT, where r is the FFT radix. For high radices [19], a hardware-efficient fully parallel FFT can reduce significantly the hardware cost of the PE in the iterative FFT.…”

Section: Introductionmentioning

confidence: 99%

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

Garrido

Möller

Kumm

2019

IEEE Trans. Circuits Syst. I

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“…Various hardware architectures have been proposed for implementing FFT algorithms [3][4][5][6][7][8][9][10][11]. However, many of the previously published designs are either large and high-throughput or relatively small, but rather low-throughput.…”

Section: Introductionmentioning

confidence: 99%

Compact and high‐throughput parameterisable architectures for memory‐based FFT algorithms

Valencia

Alimohammad

2019

IET Circuits, Devices & Systems

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Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.

show abstract

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

Cited by 38 publications

References 13 publications

Distributed-Memory-Based FFT Architecture and FPGA Implementations

Distributed-Memory-Based FFT Architecture and FPGA Implementations

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

Compact and high‐throughput parameterisable architectures for memory‐based FFT algorithms

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