A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

“…Recent work at nominal voltages has replaced embedded SRAM with DRAM to reduce cost [40]. The same opportunity exists at lower voltage and recent work aims to implement DRAM designs in logic compatible technologies that do not require out-of-range voltage biases [41], [42].…”

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency

“…3. Refresh takes place automatically in the background instead of requiring a system refresh instruction every 100 cycles [5]. Due to the 8x smaller sub-arrays than [6] there is a low probability of collision between refresh and random system accesses, which permits SRAM-like access patterns.…”

Three Dimensional integration - Considerations for memory applications

“…6, employs a face-to-face chip stacking with >1K TSV and >2K mini-bump connection as described in section II. The top 128Mb and the bottom 96Mb memories employ a P7 TM [7] style 6 transistor micro-sense amplifier (6T µSA) design and a Cu-45 TM [8] cross-coupled (CSA) version, respectively, both with 0.039µm 2 IBM High-K deep trench capacitor cells. The bump image on the front side and the grind-side are identical, allowing us to use a common probe card and module.…”