A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor

Wendell, D.; Lin, Jer; Kaushik, P.; Seshadri, S.; Wang, A.; Sundararaman, Vijayaraghavan; Wang, P.; McIntyre, H.; Kim, S.; Hsu, W.-J.; Park, H.; Levinsky, G.; Lu, J.; Chirania, M.; Heald, R.; Lazar, P.

doi:10.1109/isscc.2004.1332596

Cited by 11 publications

(9 citation statements)

References 3 publications

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“…With modest toggle rates, small to modest access rates for typical configurations found in our benchmarks, and a modest bus frequency of 250MHz, we conclude that interdie interconnect power contributes very little to overall power consumption. These results suggest on-chip DRAM can easily provide enough memory bandwidth compared to an L2 cache, as noted in Laudon [2005] and Wendell et al [2004]. Average access latency for SDRAM and DDR2 DRAM is estimated to be t RCD +t C AS , where t RCD denotes RAS to CAS delay and t C AS denotes CAS delay.…”

Section: Estimating Power and Areasupporting

confidence: 55%

“…We expect the additional area and power overhead for 64-bit support in a PicoServer core to be modest when we look at the additional area and power overhead for 64-bit support in commercially available cores like MIPS and Xeon. As for the L2 cache, we referred to Wendell et al [2004] and scaled the area and power numbers generated from actual measurements. We assumed the power numbers in Wendell et al [2004] were generated when the cache-access rate was 100%.…”

Section: Estimating Power and Areamentioning

confidence: 99%

“…As for the L2 cache, we referred to Wendell et al [2004] and scaled the area and power numbers generated from actual measurements. We assumed the power numbers in Wendell et al [2004] were generated when the cache-access rate was 100%. Therefore, we scaled the L2 cache power by size and access Gupta et al [2004], and Rahman and Reif [2000] as typical of 3D stacking interconnects.…”

Section: Estimating Power and Areamentioning

confidence: 99%

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PicoServer

Kgil

Саиди

Binkert

et al. 2008

J. Emerg. Technol. Comput. Syst.

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This article extends our prior work to show that a straightforward use of 3D stacking technology enables the design of compact energy-efficient servers. Our proposed architecture, called PicoServer, employs 3D technology to bond one die containing several simple, slow processing cores to multiple memory dies sufficient for a primary memory. The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency means that thermal constraints, a concern with 3D stacking, are easily satisfied. We extend our original analysis on PicoServer to include: (1) a wider set of server workloads, (2) the impact of multithreading, and (3) the on-chip DRAM architecture and system memory usage. PicoServer is intentionally simple, requiring only the simplest form of 3D technology where die are

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Section: Estimating Power and Areasupporting

confidence: 55%

Section: Estimating Power and Areamentioning

confidence: 99%

Section: Estimating Power and Areamentioning

confidence: 99%

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PicoServer

Kgil

Саиди

Binkert

et al. 2008

J. Emerg. Technol. Comput. Syst.

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“…L2 data arrays are protected in all current high-performance processors [1,8,3,10,19,24] Since ECC protection reduces the effective vulnerability of the L2 data array to zero, the primary source of L2 vulnerability is the tag array. Figure 2 shows the vulnerability of tag addresses versus total IL1 and DL1 (data, tag, and status) vulnerability.…”

Section: Reliability Profiling Resultsmentioning

confidence: 99%

“…In addition, many modern processors implement some form of protection such as error correction codes (ECC) on their L2 data arrays [8,3,10]. However, only a few processors provide protection bits for their L2 tag arrays [1,19,24], since the extra delay imposed by ECC computation on tag bits increases cache hit and miss times. As on-chip L2 caches increase in size, the size of their tag arrays increases proportionally.…”

Section: Introductionmentioning

confidence: 99%

Vulnerability Analysis of L2 Cache Elements to Single Event Upsets

Asadi

Sridharan

Tahoori

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the probability of particle strikes in these elements is high and can significantly impact overall processor reliability. Previous work [2] has developed effective metrics to accurately measure the vulnerability of cache memory elements. Based on these metrics, we have developed a reliability-performance evaluation framework, which has been built upon the Simplescalar simulator.In this work, we focus on the reliability aspects of L1 and L2 caches. Specifically, we present algorithms for tag vulnerability computation and investigate and report in detail on the vulnerability of data, tag, and status bits in the L2 array. Experiments on SPECint2K and SPECfp2K benchmarks show that one class of error, replacement error, makes up almost 85% of the total tag vulnerability of a 1MB write-back L2 cache. In addition, the vulnerability of L2 tag-addresses significantly increases as the size of the memory address space increases. Results show that the L2 tag array can be as susceptible as first-level instruction and data caches (IL1/DL1) to soft errors.

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