A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO

Liscidini, Antonio; Mazzanti, Andrea; Tonietto, R.; Vandi, Luca; Andreani, Pietro; Castello, R.

doi:10.1109/isscc.2006.1696247

Cited by 8 publications

(4 citation statements)

References 1 publication

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“…Unlike previously reported low power GPS receivers that reduce power through current reuse [1][2][3][4], this work achieves nearly a three fold power reduction by decreasing the supply voltage to the lowest ever reported for an integrated receiver. The 250 mV supply used herein is 150 mV lower than the previous lowest [5], a 37.5% reduction.…”

Section: Introductionmentioning

confidence: 90%

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A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS

Heiberg¹,

Brown

Mayaram

et al. 2010

2010 Symposium on VLSI Circuits

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A low-IF quadrature GPS receiver consisting of a VCO, mixer and variable gain LNA is implemented in 130 nm CMOS. Consuming 352 µW from a 250 mV supply, it has the lowest supply voltage for an integrated receiver reported to date. The measured noise figure is 7.2 dB with a gain of 42 dB at a 10 MHz IF frequency. At a 1 MHz offset, the VCO phase noise is -112.4 dBc/Hz, resulting in an FoM of 187.4 dBc/Hz.

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Section: Introductionmentioning

confidence: 90%

“…In Fig. 7, the performance of the proposed 250 mV GPS receiver is summarized with a comparison to recent low power GPS receivers [1][2][3][4]. The proposed solution consumes a third of the power compared to the lowest power design while operating at a supply voltage that is four times smaller.…”

Section: Circuit Designmentioning

confidence: 99%

A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS

Heiberg¹,

Brown

Mayaram

et al. 2010

2010 Symposium on VLSI Circuits

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show abstract

“…For the application of portable wireless consumer electronics, low power consumption is especially crucial to prolong the lasting time of the battery powered devices. Current reusing techniques which share the static current of several current‐hungry modules, reduces the total power dissipation dramatically [1–3]. However, the inter‐module crosstalk cannot be completely avoided in the current reusing structures.…”

Section: Introductionmentioning

confidence: 99%

0.6‐V 2.1‐mW RF receiver based on passive mixing and master–slave common‐mode rejection technique in 65 nm CMOS

Chen

2016

Electron. lett.

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A 0.6-V 2.1-mW RF receiver with regular threshold transistors is presented. A passive mixer which is built on low-power current-buffer is designed to build the RF front-end. A master-slave operational transconductance amplifier (OTA) structure which provides sufficient common-mode rejection ratio (CMRR) by auto-adjusting the gate of the triode-region biased tail current source is proposed as the building block of the intermediate-frequency (IF) modules. The prototype of the RF receiver is designed and fabricated in Semiconductor Manufacturing International Corporation (SMIC) 65 nm CMOS process. The measurement indicates that the receiver covers a bandwidth from 1 to 1.5 GHz, achieving a voltage gain of 32 dB and a noise figure (NF) of 10 dB.

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“…So it is not a good choice for the balance of paths. References [6,7] show the quadrature LOs by two LC tanks separately. It is easy to realize, but the area occupied is huge and special layout design techniques are needed to balance the parasitic factors.…”

Section: Introductionmentioning

confidence: 99%

A 0.18 μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

Li¹,

Zhang²,

Yeqi³

et al. 2011

J. Semicond.

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This paper presents an improved merged architecture for a low-IF GNSS receiver frontend, where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO. Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented. The gain plan and noise figure are discussed. The phase noise, quadrature accuracy and power consumption are improved. The test chip is fabricated though a 0.18 m RF CMOS process. The measured noise figure is 5.4 dB on average, with a gain of 43 dB and a IIP3 of -39 dBm. The measured phase noise is better than -105 dBc/Hz at 1 MHz offset. The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.

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A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO

Cited by 8 publications

References 1 publication

A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS

A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS

0.6‐V 2.1‐mW RF receiver based on passive mixing and master–slave common‐mode rejection technique in 65 nm CMOS

A 0.18 μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

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A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO

Cited by 8 publications

References 1 publication

A 250 mV, 352 &#x00B5;W low-IF quadrature GPS receiver in 130 nm CMOS

A 250 mV, 352 &#x00B5;W low-IF quadrature GPS receiver in 130 nm CMOS

0.6‐V 2.1‐mW RF receiver based on passive mixing and master–slave common‐mode rejection technique in 65 nm CMOS

A 0.18 μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

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A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS

A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS