A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS

Zheng, Xuqiang; Ding, Hao; Zhang, Feng; Wu, Danyu; Zhou, Lei; Wu, Jin; Lv, Fangxu; Wang, Qianqian; Liu, Xinyu

doi:10.1109/jssc.2020.2987712

Cited by 29 publications

(14 citation statements)

References 25 publications

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“…Compared with [5], the proposed Tx circuit features high-quality eye diagram and less impedance mismatch. In [6] and [13], the Tx circuits achieve high data rate in a 65 nm CMOS process but they consume more power. Compared with [6], [12] and [13], the proposed Tx circuit features less impedance mismatch.…”

Section: Design Results and Discussionmentioning

confidence: 99%

A transmitting circuit with adaptive calibration of output impedance for high speed interface

Liu

Tong

2022

J. Phys.: Conf. Ser.

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A transmitting circuit for high-speed interface is proposed in this paper. Optimized 10-bit parallel to serial conversion and embedded output impedance calibration are used for enhancing the performance of this transmitting circuit. Designed with 0.18 μm CMOS, this transmitting circuit can achieve an output data rate of 1.5625 Gbps with 10-bit 156.25 MHz parallel input. The output amplitude of the current mode logic (CML) driver is 1.28 Vpp with a jitter of 24.3 ps. After adaptive calibration, the mismatch between output impedance and its expected value is within 0.5%. The active area of this entire transmitting circuit is 220.1 μm × 197.5 μm. With 1.8 V power supply, the power consumption of this transmitting circuit is 41.2 mW at 1.5625 Gbps data rate.

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Section: Design Results and Discussionmentioning

confidence: 99%

A transmitting circuit with adaptive calibration of output impedance for high speed interface

Liu

Tong

2022

J. Phys.: Conf. Ser.

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“…The proposed LSTM equalizer is a neural learning based signal equalizer without necessary to do signal pre-processing (FFE block). Current widely used solution for the transmission line signal recovering are general realized though DFE or FFE-DFE combination [31], [32], [33]. The LSTM addressed to a novel learning based equalizer which not only more suitable for high non-linear signal restore but adaptable for A deep learning based LSTM equalizer and corresponding implementation shows the effective of the deep LSTM equalizer for variable-frequency signal equalization.…”

Section: Discussionmentioning

confidence: 99%

“…There are three types of equalizers that are generally employed in the RX module. The feed-forward equalizer (FFE), the decision feedback equalizer (DFE) [5], [6], [7], and the continuoustime linear equalizer (CTLE) [8]. The FFE is dedicated to compensating the loss of the channel which is assumed to be an FIR filter with a transfer function inverse to the channel transfer function.…”

Section: Introductionmentioning

confidence: 99%

Long Short-Term Memory Neural Equalizer

Wang

et al. 2022

SSRN Journal

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A trainable neural equalizer based on Long Short-Term Memory (LSTM) neural network architecture is proposed in this paper to recover the channel output signal. The current widely used solution for the transmission line signal recovering is generally realized through DFE or FFE-DFE combination. The novel learning-based equalizer is suitable for highly non-linear signal restoration thanks to its recurrent design. The effectiveness of the LSTM equalizer is shown through an ADS simulation channel signal equalization task including a quantitative and qualitative comparison with an FFE-DFE combination. The LSTM neural network shows good equalization results compared to that of the FFE-DFE combination. The advantage of a trainable LSTM equalizer lies in its ability to learn its parameters in a flexible manner, to tackle complex scenario without any hardware modification. This can reduce the equalizer implantation cost for variant transmission channels and bring additional portability in practical applications.

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“…Ultra-high sample rate analog-to-digital converters (ADCs) operating at several tens of gigahertz are increasingly demanded in leading-edge instruments, optical communications, multiple-input multiple-output (MIMO) systems, and 6G communications [1][2][3][4][5][6]. Benefiting from the technology scale and digital architecture, successive approximation register (SAR) ADC shows prominent advantages in power efficiency and area occupation for high-speed and moderate-resolution designs.…”

Section: Introductionmentioning

confidence: 99%

A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS

Luan

Zheng

et al. 2022

Electronics

Self Cite

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This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 mm2 and consumes 432 mW power consumption.

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A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS

Cited by 29 publications

References 25 publications

A transmitting circuit with adaptive calibration of output impedance for high speed interface

A transmitting circuit with adaptive calibration of output impedance for high speed interface

Long Short-Term Memory Neural Equalizer

A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS

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