A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

Takeshima, T.; Takada, M.; Koike, Hideaki; Watanabe, H.; Koshimaru, S.; Mitake, K.; Kikuchi, W.; Tanigawa, T.; Murotani, T.; Noda, K.; Tasaka, K.; Yamanaka, Koji; Koyama, K.

doi:10.1109/4.58282

Cited by 10 publications

(1 citation statement)

References 4 publications

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“…At the sense operation of a signal (v s ) from a memory cell, ASA and a data-line pair (DL and /DL) are separated by deactivating TG [6]. After that, the low-V T NMOS preamplifier and high-V T PMOS latch are activated with driving SG and SP to V PP2 and V DD , respectively.…”

Section: B Asa Operationmentioning

confidence: 99%

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

Kotabe

Yanagawa

Takemura

et al. 2010

2010 IEEE Asian Solid-State Circuits Conference

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DL /DL SN SP M9 M10 V DD SGP Low-V T PMOS preamplifier CMOS SA M5 M7 SG Low-V T NMOS preamplifier M1 M2 M6 M8 DL /DL SP M5 SG M3 M4 M1 M2 M6 (a) (b) M11 M12 M3 M4 Figure 1. Schematic diagram: (a) previously proposed SA (SACP) and (b) proposed asymmetric cross-coupled SA (ASA). Abstract-A new sense amplifier (SA) and relevant circuits were proposed for low-power, high-speed, and small-sized 0.5-V gigabit DRAM arrays. The SA, consisting of a low-V T NMOS preamplifier and a cross-coupled high-V T PMOS latch, achieved 46% area reduction compared to our previously proposed SA with a low-V T CMOS preamplifier. Separation of the SA and a data-line pair, and overdrive of the latch achieved a restoring time of 13.4 ns and a sensing time of 6 ns. An adaptive leakage control of the preamplifier reduced the leakage current of the SA to 2% of that without the control.

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Section: B Asa Operationmentioning

confidence: 99%