A 58nm Trench DRAM Technology

Abstract

We present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS) / high-k dielectric and metal-in-collar (MIC), and lowk inter-level dielectric (ILD) are demonstrated. IntroductionAs shown in a previous paper, the trench DRAM technology can be extended down to 70nm by using a [100] rotated substrate and a checkerboard trench layout (1). For the further scaling of this trench cell architecture to sub 60nm feature sizes major technology and device challenges have to be addressed:

Scaling of a Low Capacitance Highly Selective Self Aligned Contact Process

“…Therefore the successful introduction of an oxide spacer was one of the main innovations in our DRAM technology from 90 nm down to 58 nm [3], [4].…”

“…Both disadvantages can be avoided using an integration scheme were polycrystalline Silicon (poly-Si) can be etched selectively to an oxide spacer. A novel manufacturing method was developed and tested successfully on 90, 75 and 58 nm DRAM technolology [3], [4]. In this paper the technology and scaling challenges of the highly selective low capacitance self aligned contact process are described.…”

A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

“…1., see also (1), (2). Due to the lithofriendly layout of the checkerboard (CKB) trench cell (3), (4), immersion ArF lithography can be used down to theBo vt 4Onm node without requiring double patterning. The BUDTpofD6 tth aray device structure introduced for the 58nm technology (4) to meet the retention requirement can be extended to the 40nm generation.…”

“…Due to the lithofriendly layout of the checkerboard (CKB) trench cell (3), (4), immersion ArF lithography can be used down to theBo vt 4Onm node without requiring double patterning. The BUDTpofD6 tth aray device structure introduced for the 58nm technology (4) to meet the retention requirement can be extended to the 40nm generation. The key scaling element is the new cell arrangement, placing The introduction of 3-dimensional array devices makes new the wordline in the first local interconnect layer (MO) and cell concepts possible since the array device is not formed using the gate conductor layer (GC) as array bitline.…”

Alternate hammering test for application-specific DRAMs and an industrial case study

“…Compared to the research publications on advancing the DRAM process technologies, such as trench [1] [2] [3], metalinsulator-metal [4] [5] [6], or embedded DRAM (eDRAM) [7] [8] [9], the publications on the DRAM fault models or test algorithms are relatively limited during the past decade. [10] and [11] shared their industrial experience on constructing DRAM test and testing eDRAM, respectively, but did not discuss the fault models covered by their test methods.…”