ATMs develop from early myeloid progenitors, allowing monocyte-independent ATM replenishment.

We present a 46nm 6F 2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013um2 published to date. The TiN/ W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting in an excellent array performance. The array device can be scaled down to 30nm without compromising its performance.

A high performance surrounding gate transistor (SGT) enabling sufficient static and dynamic retention time of future DRAM cells is presented. For the first time, we demonstrate a fully depleted SGT, that shows no reduction of the retention time due to the transient bipolar effect. This effect potentially prevents DRAM application of fully depleted SGTs and is therefore investigated in detail. Based on experimental results, the impact of the proposed SGT on the scalability and performance of future DRAMS is discussed.

We present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 48nm node. The key technology enablers are a new cell architecture "Wordline over Bitline" (WOB)-realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery C devices at reduced internal voltage, and the integration of a BS MIC/ HfSiO trench capacitor.

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