A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems

Bucher, Michael; Kollipara, Ravi; Su, Bruce; Gopalakrishnan, Liji; Prabhu, Kashinath; Venkatesan, Pravin Kumar; Kaviani, K.; Daly, Barry; Stonecypher, Byron; Dettloff, W.D.; Stone, Teva; Heaton, Fred; Lu, Yi; Madden, Chris; Bangalore, S.; Eble, John; Nguyễn, Nam Thành; Luo, Lei

doi:10.1109/jssc.2013.2280308

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B Lvstl Interface1

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Cited by 24 publications

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“…Moreover, this interface is terminated to ground (VSSQ) rather than VDDQ or VDDQ/2. This improves SI characteristics of the interface as the ground signal, being the lowest impedance supply in most systems, has the strongest noise immunity [5], [6].…”

Section: B Lvstl Interfacementioning

confidence: 99%

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

Song

Lee

Kim

et al. 2015

IEEE J. Solid-State Circuits

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The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

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Section: B Lvstl Interfacementioning

confidence: 99%