A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS

Fang, Deyou; Roberts, Royal A.; Nikolić, Borivoje

doi:10.1109/asscc.2006.357941

Cited by 2 publications

(2 citation statements)

References 13 publications

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“…This is due to charge injection from the access transistor onto the storage node capacitor [24], [25]. This is confirmed by adding a dummy transistor between the access transistor and the storage node as shown in Fig.…”

Section: B Ndr Device Peak Current Requirementmentioning

confidence: 76%

90 nm 32 $\times$ 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

Anisha

Park

Berger

2011

IEEE Trans. Circuits Syst. I

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Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T-2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic "1" and 0 V as a logic "0". Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6 10 5 mW per cell and dynamic power dissipation of 1 8 10 7 mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.Index Terms-Embedded memory, low power memory, negative differential resistance (NDR), resonant interband tunnel diodes, tunnel diodes, tunnel static random access memory (SRAM).

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Section: B Ndr Device Peak Current Requirementmentioning

confidence: 76%

90 nm 32 $\times$ 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

Anisha

Park

Berger

2011

IEEE Trans. Circuits Syst. I

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“…Fruitful technological advances had been made by various research teams, spanning a wide range of technical fields from system-level architecture, data compression and decompression, storage/interface circuit design, imaging strategy and optimization, [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26] to dynamics, control and fabrication of micromirror devices. [27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45] Unfortunately, the university research funding dropped in a time frame of one to two years (2006)(2007), resulting in significantly slowed progress and even technological stagnation which were reflected in overall reduction of publication activity in projection maskless lithography after 2007.…”

Section: Introductionmentioning

confidence: 99%

Past progress, current status, and future perspective of digital EUV lithography for high-resolution semiconductor manufacturing

Chen,

Song,

Gao

et al. 2024

Novel Patterning Technologies 2024

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In this paper, a general review of the past progress, current status and future perspective of MEMS/NEMS based maskless EUV digital lithography for high-resolution semiconductor manufacturing is presented. Starting from the maskless patterning resolution and throughput requirements, we shall discuss the unique characteristics of digital EUV lithography spanning from optical and system-level design, imaging methodology, writing engine, to device process development and fabrication progress achieved. The wafer scan induced image blur impacts maskless writing speed and imaging strategy. The required high demagnification and redundant multiple-pulse exposure help to enable the defect-tolerant printing. Digital EUV lithography allows multiple/sequential stitching exposures in one scanning process without throughput penalty, thus can simplify the patterning process and amplify its competitiveness in high-NA application. Moreover, its grayscale/analog imaging principle not only significantly reduces the data rate but also provides an efficient way to enhance the resolution capability. Dynamics, control and design of electrically damped MEMS/NEMS devices will be examined. A low-temperature LPCVD SiGe process for MEMS/IC integration has been developed and the micromirror fabrication results will be reviewed. It is shown that reflective nanomirrors based maskless approach is one path to cost-effective and defect-tolerant compact EUV lithography, which helps to create emerging opportunities for low-volume but cutting-edge IC applications. Potential processing challenges and scaling issues of nanomirror device technology for a timely insertion of digital EUV lithography into future advanced IC manufacturing will also be discussed.

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A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS

Cited by 2 publications

References 13 publications

90 nm 32 $\times$ 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

90 nm 32 $\times$ 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

Past progress, current status, and future perspective of digital EUV lithography for high-resolution semiconductor manufacturing

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