A 64-Mb Embedded FRAM Utilizing a 130-nm 5LM Cu/FSG Logic Process

McAdams, H.; Acklin, R.; Blake, T.G.W.; Du, Xiangwei; Eliason, J.; Fong, J.; Kraus, W.F.; Liu, D.; Madan, Siddharth; Moïse, T. S.; Natarajan, S.; Qian, N.; Qiu, Yunchen; Remack, K.; Rodríguez, J. A.; Roscher, J.; Seshadri, A.; Summerfelt, Scott R.

doi:10.1109/jssc.2004.825241

Cited by 105 publications

(33 citation statements)

References 11 publications

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“…Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.…”

mentioning

confidence: 99%

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

El-Damak

Bandyopadhyay

Chandrakasan

2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

108

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Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection. [3,4], pulse frequency modulation (PFM) regulation logic, clock generator, gain selection block that include programmable low duty cycle timers, and a voltage reference. The transistor level implementation of the SC module is shown in Figure 21.7.2a which can be reconfigured for four gain settings (1-2/3-1/2-1/3) as shown in Fig. 21.7.2b. Each module consists of two charge transfer capacitors, 1nF each, and ten switches. Since the implementation of gain settings (2/3, 1/3) requires two capacitors while (1,1/2) can be achieved with one only, thus, for the latter each module is reconfigured into two identical sub-modules running with 180 degree phase shifted clocks for further ripple reduction.The losses due to the bottom plate parasitic capacitance of on-chip capacitors usually limit the peak efficiency of the converter. These losses occur as SC converters supply power to the load through the charge and discharge of flying capacitors (C 1 and C 2 ). A direct non-desirable impact to this process is the charge and discharge of the bottom plate parasitic capacitance, αC, every clock cycle [2]. As an example, for gain setting 1/2, the converter charges C 1 to (V in -V out ) in phase 1 and discharges it to V out in phase 2. In companion to this process the bottom plate capacitance gets charged to V out and discharged to ground wasting an energy of αC 1 V out 2 per cycle where α is technology dependent (the same process applied for capacitor C 2 but with the reverse order of phases). Highly efficient conversion is achieved by utilizing the ferroelectric capacitors, that posses extremely low bottom plate parasitics, for charge transfer. In addition, the architectures utilized for each gain setting are selected to minimize the voltage swing across the bottom plate capacitors for maximizing efficiency. Since the output load current is directly proportion...

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mentioning

confidence: 99%

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

El-Damak

Bandyopadhyay

Chandrakasan

2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

108

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“…The data in [8] suggests that the electric field from 0.6 V of bias in this work's technology will require over 10µs to develop 80% of the signal. On the other hand, [9] has shown 1.2 V or higher extracts most signal under 100ns.…”

Section: Introductionmentioning

confidence: 91%

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

Qazi

Amerasekera

Chandrakasan

2014

IEEE J. Solid-State Circuits

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In order to realize a digital system with no distinction between "on" and "off," computational state must be stored in non-volatile memory elements. If the energy cost and time cost of managing computational state in nonvolatile memory can be lowered to the microsecond and picojoule per bit level, such a system could operate from unreliable harvested energy, never requiring a reboot. This work presents a nonvolatile D flip-flop (NVDFF) designed in 0.13 µm CMOS that retains state in ferroelectric capacitors during sporadic power loss. The NVDFF is integrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying power management unit automatically saves and restores state based on the status of a one-bit indicator of energy availability. Correct operation has been verified over power cycle intervals from 4.8 µs to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are statistical measurements across 21,000 NVDFFs to validate the capability of the circuit to achieve the requisite 10 ppm failure rate for embedded system applications.

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“…A cell factor decrease is achieved by building the ferroelectric capacitor on top of a plug that contacts an underlying access transistor. For the capacitor-on-plug (COP) architecture, a cell size of 18F 2 was achieved and it was used to demonstrate 4 and 64 Mbyte memories [9,10]. An approach for circumventing the intrinsic limitations of 2T2C and 1T1C type memories to read/write endurance and memory unit cell size was to employ a nondestructive readout of the nonvolatile ferroelectric capacitor polarization state.…”

Section: Ferroelectric Memory Structuresmentioning

confidence: 99%

Recent Development in Polymer Ferroelectric Field Effect Transistor Memory

Park¹,

Jeong²,

Chang³

et al. 2008

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metalferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.

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A 64-Mb Embedded FRAM Utilizing a 130-nm 5LM Cu/FSG Logic Process

Cited by 105 publications

References 11 publications

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

Recent Development in Polymer Ferroelectric Field Effect Transistor Memory

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