A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 μm/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

Nakai, S.; Kojima, M.; Misawa, N.; Miyajima, M.; Asai, Satoru; Inagaki, Satoshi; Iba, Yoshihisa; Ohba, Takayuki; Kase, M.; Kitada, Hideki; Satoh, Shuichi; Sugiura, Iwao; Sugimoto, Fumitoshi; Setta, Yuji; Tanaka, Tetsu; Tamura, N.; Nakaishi, Masafumi; Nakata, Yoshihiro; Nakahira, J.; Nishikawa, Naofumi; Hasegawa, Akira; Fukuyama, S.; Fujita, K.; Hosaka, K.; Horiguchi, N.; Matsuyama, Hideya; Minami, T.; Minamizawa, M.; Morioka, Hiroshi; Yano, Ei; Yamaguchi, Akio; Watanabe, K.; Nakamura, Tomoji; Sugii, T.

doi:10.1109/iedm.2003.1269280

Cited by 12 publications

(6 citation statements)

References 5 publications

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“…Since the electrical characteristics of sub-10 nm copper wires do not exist in the literature, the resistivity of copper was extrapolated from Srivastava's model on 1.4 aspect ratio wires [35]. Figure 7 shows the resistivity of copper as a function of wire width for aspect ratios 1.4 and 1.6, and also contains experimental results for comparison purposes [36][37][38][39][40]; 18 μ cm resistivity is subsequently used to calculate the sheet resistance for 10 nm wide interconnects. Similarly, the contact resistance was extrapolated from experimental data on 100 nm and larger via diameters and resulted in 17.7 for each metal contact to the drain and source regions, as shown in figure 8 [37][38][39][40].…”

Section: Layout Features and Local Interconnectivitymentioning

confidence: 99%

“…Figure 7 shows the resistivity of copper as a function of wire width for aspect ratios 1.4 and 1.6, and also contains experimental results for comparison purposes [36][37][38][39][40]; 18 μ cm resistivity is subsequently used to calculate the sheet resistance for 10 nm wide interconnects. Similarly, the contact resistance was extrapolated from experimental data on 100 nm and larger via diameters and resulted in 17.7 for each metal contact to the drain and source regions, as shown in figure 8 [37][38][39][40]. The contact resistance and wire resistivity are extracted either from a technology that supports 100 nm wire features or extrapolated from a simplified scattering model that does not take into account crucial scattering mechanisms such as interface (wire surface) and grain boundary scattering [41].…”

Section: Layout Features and Local Interconnectivitymentioning

confidence: 99%

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The design of a new spiking neuron using dual work function silicon nanowire transistors

Bindal¹,

Hamedi-Hagh²

2007

Nanotechnology

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A new spike neuron cell is designed using vertically grown, undoped silicon nanowire transistors. This study presents an entire design cycle from designing and optimizing vertical nanowire transistors for minimal power dissipation to realizing a neuron cell and measuring its dynamic power consumption, performance and layout area. The design cycle starts with determining individual metal gate work functions for NMOS and PMOS transistors as a function of wire radius to produce a 300 mV threshold voltage. The wire radius and effective channel length are subsequently varied to find a common body geometry for both transistors that yields smaller than 1 pA OFF current while producing maximum drive currents. A spike neuron cell is subsequently built using these transistors to measure its transient performance, power dissipation and layout area. Post-layout simulation results indicate that the neuron consumes 0.397 µW to generate a +1 V and 1.12 µW to generate a −1 V output pulse for a fan-out of five synapses at 500 MHz; the power dissipation increases by approximately 3 nW for each additional synapse at the output for generating either pulse. The neuron circuit occupies approximately 0.27 µm2.

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Section: Layout Features and Local Interconnectivitymentioning

confidence: 99%

Section: Layout Features and Local Interconnectivitymentioning

confidence: 99%

The design of a new spiking neuron using dual work function silicon nanowire transistors

Bindal¹,

Hamedi-Hagh²

2007

Nanotechnology

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“…However, we have found the proposed technique to substantially reduce leakage for the two 130-nm and two 90-nm industrial processes that we investigated. Recent reports from leading integrated device manufacturers (IDMs) indicate that SCE continues to dominate V th roll-off characteristics at the 65-and 45-nm technology nodes [6], [16], [19], [20]. However, we note that the V th roll-off curve must be understood to assess the feasibility of this approach and to determine reasonable increases for the gate length.…”

Section: Introductionmentioning

confidence: 99%

Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking

Kahng

Reda

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer can vary by as much as 20×. Previously proposed techniques for leakage-power reduction include the use of multiple supply and gate threshold voltages, and the assignment of input values to inactive gates, such that leakage is minimized.The additional design space afforded by the biasing of device gate lengths to reduce chip leakage power and its variability is studied. It is well known that leakage power decreases exponentially and delay increases linearly with increasing gate length. Thus, it is possible to increase gate length only marginally to take advantage of the exponential leakage reduction, while impairing performance only linearly. From a design-flow standpoint, the use of only slight increases in gate length preserves both pin and layout compatibility; therefore, the authors' technique can be applied as a postlayout enhancement step. The authors apply gate-length biasing only to those devices that do not appear in critical paths, thus assuring zero or negligible degradation in chip performance. To highlight the value of the technique, the multithreshold voltage technique, which is widely used for leakage reduction, is first applied and then gate-length biasing is used to show further reduction in leakage.Experimental results show that gate-length biasing reduces leakage by 24%-38% for the most commonly used cells, while incurring delay penalties of under 10%. Selective gate-length biasing at the circuit level reduces circuit leakage by up to 30% with no delay penalty. Leakage variability is reduced significantly by up to 41%, which may lead to substantial improvements in the manufacturing yield and the product cost. The use of gate-length biasing for leakage optimization of cell instances is also assessed, in which: 1) not all timing arcs are timing critical and/or 2) the rise and fall transitions are not both timing critical at the same time.

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“…However, we have found gate-length biasing to significantly reduce leakage for all the two 130nm and two 90nm processes that we have seen so far (excluding BPTM). Recent reports from leading integrated design and manufacturing (IDM) houses indicate SCE to dominate the V th roll-off curve at least until the 45nm technology node [10,8,4,11]. We, however, note that the V th roll-off curve must be understood to assess the feasibility of this approach.…”

Section: Introductionmentioning

confidence: 92%

“…Other recently proposed runtime leakage reduction techniques include gate-length biasing [5] and adaptive body biasing. Gate-length biasing has attracted a lot of interest and several IDMs have recently published papers on the use and behavior of biasing [4,7,8,11] Multi-threshold voltage designs offer high performance with low runtime and standby leakage power. Low V th devices offer high performance but are leakier.…”

Section: Introductionmentioning

confidence: 99%

Impact of Gate-Length Biasing on Threshold-Voltage Selection

Kahng

Muddu

Sharma

7th International Symposium on Quality Electronic Design (ISQED'06)

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Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly reduce their leakage current for a small delay penalty. The technique was shown to work effectively with multi-thresholdvoltage assignment, the only mainstream approach for runtime leakage reduction. Typically, designers use threshold voltages selected by the foundries to optimize their designs. Higher threshold-voltage devices, that are less leaky but slow, are assigned to non-critical paths and lower threshold-voltage devices, that are fast but leaky, are assigned to critical paths.In this paper we study the effect of modifying threshold voltages set by the foundry on leakage reduction achieved on three large, real-world designs. We assess the impact of the availability of gate-length biasing on threshold voltage selection. We achieve comparable leakage reductions when foundry-set dual threshold voltages are used with biasing than when foundry-set triple threshold voltages are used without biasing. Our results indicate that leakage reductions can be improved if threshold voltages are carefully chosen considering the availability of gate-length biasing. We also observe that foundry-set threshold voltages are not optimal for achieving best possible leakage reductions.

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A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 μm/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

Cited by 12 publications

References 5 publications

The design of a new spiking neuron using dual work function silicon nanowire transistors

The design of a new spiking neuron using dual work function silicon nanowire transistors

Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking

Impact of Gate-Length Biasing on Threshold-Voltage Selection

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