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45nm-node multilevel Cu interconnects w i t h porous-ultia-low-k have successfully been integrated. Key features to realize 45nm-node interconnects are as follows: I ) porous ultra-low-k material NCS pano-Clustering Silica [I]) has been applied to both wire-level and via-level dielectrics (what we call hlI-NCS structure), and its sufficient robustness has been demonstmted. 2) 70-nm vias have been formed by high-NA 193nm lithography w i t h fine-tuned model-based OPC and multi-hard-mask dual-damascene process. More than 90% yields of 1M via chains have been obtained. 3) Good TDDB (Time-Dependent DielectricBreakdown) characteristics of 70nm Wire spacing filled w i t h NCS has been achieved. Because it is considered that applied-voltage (Vdd) of a 45nm-node technology will be almost the same as that of the previous technology, the dielectrics have to endure the high electrical field. NCS in Cu wiring has excellent insulating property without any pore sealing materials which cause either keff value or actual wire width to be worse.

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Defects in the normalInGaAsP‐normalInP multiepitaxial layers on the normalInP (111)P substrate were investigated using chemical etching techniques. Threading dislocations, stacking faults, dislocation rosettes, and dislocation crowds were revealed on normalInP epitaxial layers by the AB etch at 60°C. They were identified from their etch features and it was suggested that dislocation rosettes and crowds were caused by localized mismatch stress.

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uni-axial strain and low resistance NiSi technique, enhanced by a slit under the slim and high young's modulus(YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (R sd ) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% R sd reduction, enhancements of 19 and 14% and I on (@I off = 5 nA/µm) of 620 and 830 µA/µm were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% R sd reduction, the enhancements of 32 and 22% and I on of 330 and 440 µA/µm were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best I on -I off tradeoff characteristics among the recent LOP transistors. IntroductionHuge markets for battery-operated applications, multi-core LSIs and SoCs with low cost packaging, require both performance enhancement and reduction of the operation power of integrated transistors. In order to find a solution to these requirements, we developed high-performance LOP transistors characterized by low V dd operation to reduce the dynamic (CV dd