As the degree of large-scale integration (LSI) increases, the area of a single transistor will diminish and the density of transistors will increase. Accordingly, technology for high-density wiring to interconnect the huge number of transistors is needed because transistors cannot perform any useful functions without interconnects and electrodes. For advanced microprocessor chips with a sub-half-micron design rule and at least four interconnect layers, the minimum width of the interconnects becomes less than 0.35 μm.Aluminum or an aluminum alloy is now generally used as the interconnect material in LSI circuits because the physical and chemical properties of aluminum are compatible with current LSI processing: Aluminum forms a thin protective oxide film that withstands various thermal processes; it has relatively low electrical resistivity and halide compounds with a relatively high vapor pressure which are suitable for reactive ion etching (RIE), and it is an inexpensive material. The reliability of aluminum interconnects, however, is a major concern for maintaining the total reliability of advanced LSI. Because of its relatively low melting point, aluminum as an interconnect material is susceptible to stress- and electromigration, which leads to open failure of the interconnect. It is well-known that these failure modes are accelerated by decreasing the width and thickness of the interconnects. Hence, use of aluminum interconnects may be limited for future sub-half-micron LSIs.

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45nm-node multilevel Cu interconnects w i t h porous-ultia-low-k have successfully been integrated. Key features to realize 45nm-node interconnects are as follows: I ) porous ultra-low-k material NCS pano-Clustering Silica [I]) has been applied to both wire-level and via-level dielectrics (what we call hlI-NCS structure), and its sufficient robustness has been demonstmted. 2) 70-nm vias have been formed by high-NA 193nm lithography w i t h fine-tuned model-based OPC and multi-hard-mask dual-damascene process. More than 90% yields of 1M via chains have been obtained. 3) Good TDDB (Time-Dependent DielectricBreakdown) characteristics of 70nm Wire spacing filled w i t h NCS has been achieved. Because it is considered that applied-voltage (Vdd) of a 45nm-node technology will be almost the same as that of the previous technology, the dielectrics have to endure the high electrical field. NCS in Cu wiring has excellent insulating property without any pore sealing materials which cause either keff value or actual wire width to be worse.

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