0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application

Takao, Yoshihiro; Nakai, S.; Tagawa, Y.; Otsuka, Shun; Sambonsugi, Y.; Sugiyama, K.; Oota, H.; Iriyama, Yu; Nanjyo, R.; Nagai, Hideo; Naitoh, K.; Nakamura, Ryozo; Sekino, Shoji; Yamanoue, A.; Horiguchi, N.; Yamamoto, Takuji; Kojima, M.; Satoh, Shuichi; Sugii, T.; Kase, M.; Suzuki, Kazuki; Nakaishi, Masafumi; Miyajima, M.; Ohba, Takayuki; Hanyu, Isamu; Sugatani, Shinji

doi:10.1109/vlsit.2002.1015417

Cited by 4 publications

(2 citation statements)

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“…We prepared the sub-50 nm p-MOSFETs with the sidewall notches well controlled 4) to evaluate the effect of the bottom shape in the offset spacer on the 2-D carrier profile around the SDE region. Two p-MOSFET samples were fabricated under a process for planar complementary metal oxide semiconductor (CMOS) devices with sidewall notches, as shown in Fig.…”

Section: Electrical Characteristics Of Sub-50 Nm P-mosfetsmentioning

confidence: 99%

Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors

Fukutome¹,

Saiki²,

Nakamura³

et al. 2006

jjap

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We have directly measured the effect of the bottom shape in the offset spacer on the two-dimensional (2-D) carrier profiles of the sub-50 nm p-metal oxide semiconductor field-effect transistors (MOSFETs). It has been observed that the doping profile of the Sb pocket implanted with a high angle tilt is very sensitive to the bottom shape of the notched offset spacer. It has been confirmed that the Sb pocket deeply implanted leads to the decrease of 2 nm in the average overlap length of the extension region at a depth of 5 nm when the bottom shape is slightly upped at the notched offset spacer. The increased effective channel length is considered to enhance the dependence of the threshold voltage on the body bias voltage. Moreover, it is considered from the measured carrier profiles that the reduction in carrier concentration in the top channel region lowers the threshold voltage.

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Section: Electrical Characteristics Of Sub-50 Nm P-mosfetsmentioning

confidence: 99%

Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors

Fukutome¹,

Saiki²,

Nakamura³

et al. 2006

jjap

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“…the circuit illustrated in Fig. 3 was designed and fabricated with 90 nm CMOS technology of FUJITSU [11) [12]. Fig.…”

Section: Vcdl Of Dllf (Left) and Vcdl Of Dllz (Right)mentioning

confidence: 99%

High-resolution on-chip propagation delay detector for measuring within-chip variation

Matsumoto

2005

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

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We describe a circuit that can measure the propagation delay of a logic circuit directly even for one fan-out 1 inverter of CMOS 90 nm node technology. We obtained high-resolution (I ps) by converting the propagation delay to the control voltage of the voltage-controlled delay line (VCDL) in Delay-Locked Loop (DLL). The circuit was fabricated with 90 nm CMOS technology and we have verified the function. This circuit can be used for measuring within-chip and chip-to-chip variation that is important for design automation in sub-lOOnm technolog.

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Requirements for ultra-thin-film devices and new materials for the CMOS roadmap

Fenouillet-Béranger

Skotnicki

Monfray

et al. 2004

Solid-State Electronics

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0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application

Cited by 4 publications

References 0 publications

Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors

Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors

High-resolution on-chip propagation delay detector for measuring within-chip variation

Requirements for ultra-thin-film devices and new materials for the CMOS roadmap

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