A 65nm CMOS EDGE/UMTS/WLAN tri-mode four-channel time-interleaved &amp;#x03A3;&amp;#x0394; ADC

Fakhoury, Hussein; Jabbour, Chadi; Khushk, Hasham Ahmed; Van-Tam-Nguyen,; Loumeau, Patrick

doi:10.1109/newcas.2009.5290508

Cited by 3 publications

(1 citation statement)

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“…Its advantage is that it does not need digital pre-filtering to cancel first stage quantization noise as is the case in traditional cascade sigma-delta. Modulator coefficients are chosen as a compromise between modulator stability, suppression of quantization noise, unity signal transfer function (STF) and maximum hardware reusability [18].…”

Section: Principlementioning

confidence: 99%

A new interpolation technique for time interleaved $$\Upsigma\Updelta$$ A/D converters

Beydoun

Jabbour

Nguyen

et al. 2011

Analog Integr Circ Sig Process

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Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65 nm CMOS process.

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Section: Principlementioning

confidence: 99%