A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-<i>N</i> Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

Santiccioli, Alessio; Mercandelli, Mario; Bertulessi, Luca; Parisi, Angelo; Cherniak, Dmytro; Lacaita, A.L.; Samori, Carlo; Levantino, Salvatore

doi:10.1109/jssc.2020.3019344

Cited by 54 publications

(12 citation statements)

References 32 publications

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“…For oscillators of ultralow flicker PN [44]- [50], their "instantaneous period jitter," T osc [k], mainly induced by the 9 The cross products of two T osc at different harmonics of f ref could be practically neglected as compared to the self-squares. 10 The replica appearing at m f ref (m ≥ N/2) could be seen mathematically as that at m − N ; thus, the replicas cause the same influence on the upper sideband as on the lower sideband of the original PN [31], [43]. 11 This is a justification as to why the original explanation of SS-PLL's low PN mechanism highlighting "PD/CP noise not multiplied by N 2 " due to the divider-less arrangement [3] is not entirely correct since the 1/N factor could be also added in the feedback path of the divider-less PLL for the phase domain normalization from the oscillator's to the reference's sampling rate.…”

Section: B Downsampling Of Oscillator Timestampsmentioning

confidence: 99%

“…1, the rms jitter for a 5G PLL (in both sub-6 GHz and mmW) must be below 100 fs. There are two technical routes toward achieving the sub-100-fs rms jitter: 1) various sampling techniques [3]- [10] relying on a high phase detector (PD) gain (e.g., sub-sampling This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/…”

mentioning

confidence: 99%

“…[3]- [7] by exploiting sharp edges of the oscillator's sinusoidal waveform, 1 sampling an RC waveform at the reference rate [8], and a bang-bang operation [10]) to increase the loop bandwidth and suppress the oscillator's PN while using a reference of high-frequency and low PN [10]; and 2) injection locking (IL), including phase realigning techniques [13]- [21] based on the oscillator's instantaneous phase correction (with virtually no loop delay). The intrinsic PN mechanisms in the above two techniques are entirely different: the former tunes the oscillator's frequency (e.g., via the LC-tank capacitance), while the latter changes the instantaneous phase (e.g., changing the charge in an LC-tank).…”

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confidence: 99%

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A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

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Section: B Downsampling Of Oscillator Timestampsmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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“…This limitation makes it difficult to realize a low-jitter frequency synthesizer with a low f REF source [2]. Thus, a high f REF source is more popular than a lower one [10]- [12] in ultra-low-jitter PLL applications.…”

Section: Introductionmentioning

confidence: 99%

“…Among those block gain settings, the PD's gain is sensitive to other blocks' noise and usually dominates the performance of achievable BW loop for a given PD frequency. Clock rising edge timing comparison by the digital bang-bang phase detector (BBPD) [10], [21] or multi-bit TDC [22], [23] attracts attention in the literature for their simple implementation and good jitter performance, as illustrated in the left-hand side of Fig. 1(a).…”

Section: Introductionmentioning

confidence: 99%

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Qiu

Sun

Liu

et al. 2021

IEEE J. Solid-State Circuits

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In this article, a mixed-signal, 32-kHz referencebased 2.4-GHz fractional-N over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional 1× sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digitalto-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm 2 , and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-N modes with the loop-bandwidth (BW loop ) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively.

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Digital Phase‐Locked Loop

2024

Encyclopedia of RF and Microwave Engineering

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This chapter overviews the topology of digital phase‐locked loop (DPLL) structure and extensive advantages compared to it analog counterpart, that is, the conventional charge‐pump PLL. The basic operation and implementation of the DPLL building block are introduced, including the digital quantizer, digital embodiment and digitally controlled oscillator. The ‐domain model of the DPLL loop is discussed to provide a high‐level picture how to analyze the digital loop dynamic. To emphasize the feasibility of the potential digital‐signal processing (DSP) techniques embedded in the DPLL architecture, the DSP module is studied with a spur cancellation scheme as a representative example. The rationale of the DSP engine and DPLL implementation with silicon proof is demonstrated to validate the effectiveness of the DSP technique. Finally, multiple state‐of‐the‐art DPLLs (only to name a few because of the length requirement) with various DSP capabilities are reviewed. Those prior works with unprecedentedly performance imply the potential of this digital architecture to be adopted for the integrated circuit design community.

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A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

Cited by 54 publications

References 32 publications

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Digital Phase‐Locked Loop

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