A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface

Jung, Dong Hoon; Ryu, Kyung Ho; Jung, Seong‐Ook

doi:10.1109/tce.2010.5681119

Cited by 3 publications

(2 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…D ELAY-LOCKED loops (DLLs) are widely used in memory applications to perform tasks such as clock synchronization and strobe signal generation [1]- [6]; for instance, a 90°phase-shift DLL is used to shift the data strobe signal by 90°for data sampling [7]- [9]. As the data-rate requirements of dynamic RAM (DRAM) increase, the timing margin for data sampling in the DRAM I/O becomes worse; correspondingly, highly accurate 90°phase shifting and low-jitter performance are significant DLL design factors.…”

Section: Introductionmentioning

confidence: 99%

All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme

Jung

Ryu

Park

2016

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

This paper proposes a 90°phase-shift delay-locked loop (DLL) used in dynamic RAM for data sampling clock generation. The proposed DLL alleviates process variation issues, which are mainly caused by the mismatch between the delay line segments in the previous 90°phase-shift DLLs, and reduces area by adopting a multiplying DLL-based structure. In addition, a novel jitter suppression scheme is also proposed to suppress control code dithering. A stochastic analysis is performed to evaluate the effectiveness of the proposed dithering jitter suppression. The proposed DLL is fabricated using a 45-nm CMOS process on an active area of 69.9 µm × 49.3 µm and utilizes a 1.1 V supply voltage. The proposed DLL has an operating frequency ranging from 500 to 800 MHz and consumes 1.32 mW at 800 MHz. The measured rms and peak-to-peak output jitters are improved by 5.42% to 18.75% and 5.52% to 18.31%, respectively, in the entire operating frequency range.Index Terms-90°phase shift, delay-locked loops (DLLs), dithering jitter suppression, dynamic RAM (DRAM), low jitter.

show abstract

Section: Introductionmentioning

confidence: 99%

All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme

Jung

Ryu

Park

2016

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…According to the International Technology Roadmap for Semiconductors (ITRS) 2010 report, the performance of the SoC will improve 100-fold in the next decade, and the increase in power consumption will also be five times or more [1]. However, since the battery capacity will not meet the rapid increase in power consumption of the SoC in the near future, the future of the hand-held device market is vague without the technology for reducing the SoC's power consumption [2], [3]. In this situation, along with the growing interest in eco-friendly technologies worldwide, the low-power green SoC design technique has become the main trend in SoC design.…”

Section: Introductionmentioning

confidence: 99%

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator

Ryu

Jung

2012

IEEE Trans. Circuits Syst. I

Self Cite

View full text Add to dashboard Cite

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-m process technology. It has an area of 0.035 mm and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.Index Terms-DLL, dual edge triggered, jitter, lock speed, loop stability.

show abstract