A Background Correction Technique for Timing Errors in Time-Interleaved Analog-to-Digital Converters.

Background analog and mixed signal calibration system for time-interleaved ADC

“…In normal operation, M channels are working normally and one of them is under calibration (ADC iUT ) as in [13][14][15][16]. In these publications, the extra ADC operates at sampling frequency of f s =ðM þ 1Þ.…”

A Jittered-Sampling Correction Technique for ADCs

“…The former is easily removed by the use of a limiter, or inherently clamped by factors including limited supply rails voltage, whereas any fluctuation in the phase jitters the oscillation and persists indefinitely [24]. It is convenient to describe timing errors as 2 entities, namely clock skew and clock jitter [25]. Clock skew is a deterministic drift of a clock signal that is either fixed or …”

“…As presented so far, much effort has been done in analysing and modelling the origins and effects of jitter, in contrast, not much has been done to correct the effects of timing mismatches [25].…”

“…This is caused by clock path mismatches [22,25,34,35]. The mismatch between each channels are estimated through an extra calibration circuit that runs in background without interrupting the conversion.…”

“…The mismatch between each channels are estimated through an extra calibration circuit that runs in background without interrupting the conversion. The correction is then performed in digital domain through an interpolation method [25]. This implies that performing envelope detection on ( ) v t ɺ , and ( ) t αɺ can be obtained.…”