A bulk CMOS 20MS/s 7b flash ADC

Fujita, Yasuhiko; Masuda, E.; Sakamoto, S.; Sakaue, T.; Sato, Yukihiko

doi:10.1109/isscc.1984.1156643

Cited by 4 publications

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Analysis of reference‐tap‐voltage fluctuation in flash A/D converter

Nakaya

Kumamoto

Miki

et al. 1987

Electron Comm Jpn Pt II

View full text Add to dashboard Cite

To improve the speed and accuracy of the CMOS flash A/D converter using a copper‐type comparator, an analysis has been performed for the voltage variation at each reference terminal of the ladder resistor providing a reference voltage. A model has been developed in which the circuit made of the ladder resistor and the input capacitance of the comparator is treated as a distributed network. A theoretical formula is derived which analytically provides transient behavior of each reference terminal voltage due to change in the comparator. With this formula, it is found that the maximum error of the reference terminal voltage occurs when the input voltage is either 0 or V ref. The error decreases exponentially with reduction of ladder resistors and comparator input capacitances and with increase of time. It is found that the product of the ladder resistor and the comparator input capacitance between adjacent terminals must be less than 5 × 10−13 F.Ω in order to obtain an 8 bit A/D converter with 20 MS/s. Variation is decreased if the midpoint of the ladder resistor is fixed. For instance, when the midpoint is fixed, the product of the ladder resistor and the comparator input capacitance is allowed to increase up to 2 × 10−12 F.Ω.

show abstract