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T h e T X 2 processor zs the second zmplementatzon an the Toshzba TLCSSOOOO/TX semes of 32-bzt mzcroprocessors based on the TRON[l] speczjicatzon. T h e TX2 mzcro-archztecture defines jive functzonal m a t s whach zmplement a four-stage pzpehne. Baszc znstructaons wzth regzster-regaster operatzon are executed an a szngle cycle wath a sangde step of macrocode. T h e TX2 h a s a performance of 25 MIPS and executes about 20,000 dhystones/second at 25MHz wath zero waat external bus cycle. Deszgn of the T X 2 as based o n full custom LSI deszgn methodology. To zncrease the operatzng frequency of the CISC macroprocessor TX2, tzmzng design based on statzc path delay analysts was performed. A s a result , hzgh speed processor has been achzeved.

THE RAPID ADVANCEMENT of the microprocessor in the field of analog data acquisition systems has increased the demand for low-cost high-performance microprocessor-compatible A/D converters. To meet the demand a single-chip C'MOS 12-bit A/D converter has been developed using a standard metal gated CMOS process.The block diagram of the A/D converter with full external components is shown in Figure 1. To interface with a microprocessor* and to reduce the total system cost, the device contains an 8-channel analog multiplexer, a channel-address decoding logic, a read/write interface logic, an integrating A/D conversion circuit, and tri-state output buffers on a single-chip powered by a single 5V supply. The device is controlled directly by the microprocessor through software. At the beginning of write operation, one channel is addressed out of the eight inputs through bidirectional bus lines. End signal is received as an interrupt by the microprocessor when the conversion is complete. Data access time from the start of read operation to the data valid on bus lines measures 200ns typically, with a load of 100pF.The use of a relatively high clock frequency (3MHz typical inner clock which is half of the external input clock) results in a conversion time of 3.6ns.provides a unipolar and ratiometric conversion. A conversion cycle, as shown in Figure 2, consists of five phases; (0)-the integrator runs as a voltage follower with subreference %VREF input and charges its offset voltage to an external capacitor Cc;(1)-the analog ground voltage AGND is integrated after the operation of offset compensation which inserts the charged C c between %VREF and the noninverting input of the integrator in reverse polarity; (11)-reference voltage VREF is integrated for a fixed interval T2 (2048 clock counts); (111)-selected sample voltage VS is integrated for the same interval as T2, and (1V)analog ground voltage AGND is integrated for an interval T4 related to the digital output. chip dividing resistors. Note that either the absolute accuracy of the threshold voltage VC or the offset voltage of the comparator has no influence on data conversion as long as the ratio of the dividing resistors remains stable within a conversion cycle.from the signal loop between the digital and analog circuits. Kgh accuracy in the system using relatively high clock frequency has been obtained by including: (a)-counters designed to operateThe system employs an improved dual-slope technique whichThe threshold voltage VC of a comparator is supplied by on-The main factors which dominate the conversion accuracy stem __ *TLCS-12A

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