A capacitance-voltage measurement method for DMOS transistor channel length extraction

Abstract

This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 pm has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.

Power Characteristics of High Voltage LDMOS Transistors

“…The transistor channel is formed by diffusion of an additional masked self-aligned p-base implantation (extra process step compared to the CMOS-process). The channel length was measured to be 0.30ptm [2], and the gate oxide thickness is 350 A. It should be pointed out that for this type of LDMOS transistor the channel length is constant regardless of the gate length.…”

Capacitance Modelling of LDMOS Transistors

“…High voltage lateral double diffused MOS transistors can now be merged on a single chip with low power control circuitry to provide high voltage integrated circuits (HVIC's) [1,2]. The LDMOS transistors analysed in this work had a maximum voltage rating of 30V and were integrated onto a standard 0.6µm CMOS process in order to realise a 0.6µm BCDMOS technology.…”