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We present a new process flow for the integration of vertical high voltage devices on thick SOI. The creation of slip dislocations has been avoided by etching and filling the trenches at the end of the process. Thereby are the trenches not exposed to high temperature steps which trigger the creation of these defects. The electrical characteristics of the fabricated devices are not affected by these process modifications. High voltage transistors with breakdown voltages of 480 V have been fabricated with this new process.

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This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 pm has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.