A carrier-based analytical theory for negative capacitance symmetric double-gate field effect transistors and its simulation verification

Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

doi:10.1088/0022-3727/48/36/365103

Cited by 24 publications

(19 citation statements)

References 25 publications

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“…And, the latter is the typical case (low power supply and ultrasmall dimension) of state-of-the-art nanoscale devices being fabricated. This approximation has been verified in our previous work [17].…”

Section: Introductionsupporting

confidence: 82%

Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Jiang

2016

IEEE Trans. Nanotechnology

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Abstract-A short-channel negative capacitance gate-all-around tunnel field-effect transistor (NC-GAA-TFET) with a ferroelectric gate stack is proposed. Device performance is investigated by integrating three-dimensional (3D) numerical simulation and the one-dimensional (1D) Landau-Khalatnikov equation. It is shown that the NC-GAA-TFET has a steeper subthreshold swing and higher on-state current compared to conventional GAA-TFETs, and demonstrates no hysteretic behavior. Relevant analytical models, including the electrostatic potential model and the shortest tunnel path length (lsp), are developed to explain the device's operating principles and design optimization issues. Results from the analytical electrostatic potential model agree well with those of the numerical simulation. Furthermore, the analytical calculation shows that gate controllability over the channel is enhanced and the lsp value is significantly reduced as the thickness of the ferroelectric dielectric increases, resulting in better device characteristics. These results demonstrate the tremendous potential of NC-GAA-TFETs in low-power applications.Index Terms-Negative capacitance, tunnel field-effect transistor, analytical model, ferroelectric dielectric, numerical simulation, subthreshold swing.

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Section: Introductionsupporting

confidence: 82%

Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Jiang

2016

IEEE Trans. Nanotechnology

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“…The operation principle of Negative Capacitance FETs (NCFETs) has been theoretically investigated [7], [8], [9], [10]. However, previous research studies related to the operation mechanism of NCFETs have some limitations.…”

Section: Introductionmentioning

confidence: 99%

Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Saeidi

Jazaeri

Stolichnov

et al. 2016

IEEE Trans. Electron Devices

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In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14 nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain negative capacitance effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the non-hysteretic operation of negative capacitance transistors. We report a clear and significant double improvement in (i) subthreshold swing and (ii) gate overdrive, using negative capacitance effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14 nm node UTBB FDSOI-FET can operate at 0.26 V instead of 0.9 V gate voltage using negative capacitance effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the negative capacitance effect and reduce the ferroelectric's optimized thickness. A 14 nm node DG-NCFET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.

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“…Since dQ sc = dQ m , we introduce (19) in (18). After solving the integral, an analytical and explicit relation for the total charge in the ferroelectric is obtained (in depletion mode):…”

Section: A Recalling Jlfet Core Equationsmentioning

confidence: 99%

“…To the best of our knowledge, it is the most common approach to the study of negative capacitance effects with ferroelectrics [8]- [14], [16]- [18]. The simulation and modeling study of negative capacitance in the MOSFETs has been investigated in the literature [19]- [23]. Also, some studies have been done to investigate the short channel effect in inversion-mode NC FETs, a majority of them being based on detailed simulations [24]- [26].…”

Section: Introductionmentioning

confidence: 99%

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Rassekh

Sallèse

Jazaeri

et al. 2020

IEEE J. Electron Devices Soc.

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In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels. Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.

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A carrier-based analytical theory for negative capacitance symmetric double-gate field effect transistors and its simulation verification

Cited by 24 publications

References 25 publications

Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

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