A Case Study of Testing Strategy for AI SoC

Ma, Haiying; Guo, Rui; Quan, Jing; Han, Jing; Huang, Yu; Singhal, Rahul; Wu, Yang; Wen, Xin; Meng, Fanjin

doi:10.1109/itc-asia.2019.00024

Cited by 13 publications

(4 citation statements)

References 2 publications

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“…This requires additional XOR logic for output comparisons between neighboring elements and may result in an increased test area overhead. Ma et al [29] have tested an AI based SoC by broadcasting test patterns by embedded deterministic test (EDT) to the identical cores to reduce test time. These cores are isolated by IEEE 1500 wrappers and are tested by means of comparator in subsequent test modes.…”

Section: Related Workmentioning

confidence: 99%

Test Architecture for Systolic Array of Edge-Based AI Accelerator

et al. 2021

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The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT.

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Section: Related Workmentioning

confidence: 99%

Test Architecture for Systolic Array of Edge-Based AI Accelerator

et al. 2021

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“…Logic BIST based STUMPS solution can also reduce the ATE storage overhead, but it suffers from high shift power and aliasing error issues [22]. Industrial test solutions utilize homogeneity of arrays to limit ATPG effort for testing of such large arrays [23]- [28]. These solutions use broadcasting of same input test patterns to identical cores.…”

Section: Introductionmentioning

confidence: 99%

“…In the proposed method, this power difference is leveraged by combining multiple Slaves with Master into Subcores for test pattern loading. Proposed method is compared with Broadcast method[23]-[28]. In Broadcast, group of PEs are applied with test patterns (parallel) in multiple test sessions.…”

mentioning

confidence: 99%

Master-slave based test cost reduction method for DNN accelerators

Solangi

Ibtesam

Park

2021

IEICE Electron. Express

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“…Increasing coverage would require longer test times and insertion of test points in the presence of random pattern resistant faults [18]. Parallel broadcasting of test patterns to PEs/ groups of PEs is used, to shorten the test time [19]- [24]. However, shift power is still a major bottleneck and affects the overall test time.…”

Section: Introductionmentioning

confidence: 99%

Time multiplexed LBIST for in-field testing of automotive AI accelerators

Solangi

Ibtesam

Park

2021

IEICE Electron. Express

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Logic BIST is a safety mechanism, which performs testing for Automotive electronics. However, pseudorandom LBIST patterns results in increased test time and test power. In this letter, a novel time multiplexed LBIST is presented to overcome test related problems of AI accelerators. First, the accelerator array is divided into smaller sub arrays, which are tested on time multiplexed clock cycles. This: 1) improves overall test time, under the given test power limit, 2) allows reduction in shift power, under given test time limits and 3) since only one sub array is clocked at a time, the peak power is reduced.

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A Case Study of Testing Strategy for AI SoC

Cited by 13 publications

References 2 publications

Test Architecture for Systolic Array of Edge-Based AI Accelerator

Test Architecture for Systolic Array of Edge-Based AI Accelerator

Master-slave based test cost reduction method for DNN accelerators

Time multiplexed LBIST for in-field testing of automotive AI accelerators

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