A challenge of 45 nm extreme low-k chip using Cu pillar bump as 1&lt;sup&gt;st&lt;/sup&gt; interconnection

Cheng, Po‐Jen; Chung, Chi-Sheng; Pai, Tsung-Yun; Chen, D. Y.

doi:10.1109/ectc.2010.5490768

Cited by 8 publications

(6 citation statements)

References 6 publications

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“…It has been shown that the Cu pillar design is highly dependent on the mechanical property of undefill [2]. Besides, some studies also showed the effects of polyimide (PI) opening and design of Cu pillar size and structure on low-k stresses [3,4]. This study will focus on measurement and calculation of thermally-induced deformations and stresses in the Cu pillar flip chip package.…”

Section: Introductionmentioning

confidence: 97%

Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

Jhou

Tsai

et al. 2010

2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference

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When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy) and aluminum pad.The purpose of this study is to measure and calculate thermallyinduced deformations and stresses of flip-chip ball grid array (BGA) packages with a copper-pillar-bump interconnected chip inside. In the experiments, full-field Twyman-Green and moiré interferometries are used to measure out-of-plane deformations on the chip surfaces of the package during a heating process and inplane deformations on the cross-section surface of the package under a specific thermal loading, respectively. A finite element method (FEM) and Suhir's die-attachment assembly theory being validated by experimental data are employed to analyze the thermally-induced deformations and stresses of the package to gain insight into their mechanics. The experimental results show the zero-warpage temperature (or zero-stress temperatures) for this package is 115 due to the Tg of the underfill material rather than its curing temperature. It is also found that the thermal deformations of the package calculated by FEM and theory are well consistent with Twyman-Green and moiré results. Furthermore, the local stresses around the critical copper-pillar bump joint region (especially at aluminum pad and low-k layer) where the possible failures occur during the TCT are investigated in detail through the validated FEM model. The results indicate that die/substrate thickness ratio would have significant effect on the stresses at aluminum pad and low-k layer, as well as package warpage and die stress.

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Section: Introductionmentioning

confidence: 97%

Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

Jhou

Tsai

et al. 2010

2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference

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“…In recent years, thermal compression bonding has been preferred for pitch below 40 µm since reflow and placement accuracy are deemed inadequate for such fine pitch [7][8]. In this study, we focused on thermal compression bonding (TCB) to address technology requirements for the current and future processors and logic devices.…”

Section: Introductionmentioning

confidence: 99%

“…Lower current density also helps improve electro-migration at the solder interface. Further implementation of bump-on-trace (BOT) or bump-on-lead (BOL) or bump-on-package (BOP) as referred in the literature [6][7][8] is expected to significantly increase the interconnect density on the substrate leading to lower number of substrate layers, therefore reduce the package thickness and fabrication cost while simultaneously achieve the smallest form factors in all three dimensions.…”

Section: Introductionmentioning

confidence: 99%

Reliability assessment of thermally compression bonded copper pillar on organic and ceramic substrates

Bhattacharya¹,

Lewis²,

Wu³

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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The ultimate goal of this study is to address and overcome the critical barriers for implementing a low cost high yield manufacturing process using thermal compression bonding of copper pillars to a high density organic substrate with the aid of a nonconductive paste. First, a conventional reflow bonding of the copper pillars to the organic and ceramic substrate was conducted and reliability after air-to-air thermal cycling was compared for baseline evaluation. The selected test vehicle for this step was a pressure sensor module where ASIC and MEMS chips were mounted on both sides of a 6-layer organic and a 6-layer ceramic substrate using a solder paste and an underfill material. Thermal cycling of the constructed functional module showed superior reliability for the ceramic substrate compared to the organic. In the second step, a design of experiments was conducted to optimize process conditions for thermal compression bonding of the copper pillars in ASIC chips to both ceramic and organic substrates using a nonconductive paste in lieu of an underfill. The assembled substrates were thermally cycled under similar conditions to evaluate thermal reliability performance and mechanical integrity of the bonding. Results show better performance for the ceramic substrate compared to the organic. The conditions for dispensing a nonconductive paste and thermal compression bonding using an automated machine have been optimized for further evaluation and scaling up to manufacturing where dispensing of the nonconductive paste, placement of chips, and thermal compression bonding can be achieved in-situ with a single assembly tool with reduced cycle time. The substrate for high throughput manufacturing is a 3-layer (dielectric) high density organic allowing direct landing of fine pitch copper pillar to the conductor traces without any landing pads.

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“…(Baliga, 2006, Cheng et al, 2010and Gerber et al, 2011. (Heinen et al, 1989, Yeoh et al, 2006, Wang et al, 2010and Cheng et al, 2010 (Ralf et al, 2000). The manpower cost for operating the underfill stations can be assumed to be US$3000 per month.…”

Section: Discussionmentioning

confidence: 99%

“…Using brittle low-K dielectric materials to reduce on-chip interconnect parasitic capacitance in SiPs can pose serious thermomechanical reliability concerns (Heinen et al, 1989, Yeoh et al, 2006, Cheng et al, 2010, if a large CTE mismatch exist between the silicon chip (2.6 ppm/°C) and organic substrate (17 ppm/°C). Despite the adaptability of Cu pillar bump technology for high density interconnection, the high stiffness of Cu pillar remains a concern when used in low-k chip interconnection.…”

Section: Figure 22mentioning

confidence: 99%

Development of a flip-chip composite interconnection system

Wong¹

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I would like to express my heartfelt gratitude to Prof. John Pang for his guidance, mentorship and invaluable discussions throughout my research. I would like to acknowledge the Singapore Institute of Manufacturing Technology (SIMTech), A*STAR, for sponsoring this research and my special thanks Dr Lim Ser Yong for his constant encouragement. Throughout this research, I received great support from my colleagues from JTG, MMP, MTG and PMG. In particular, I would like to extend my greatest appreciation to Mr Fan Wei for assisting in the test instrumentation, Ms Lu Haijing in the plating evaluations, Dr Yi Ming in the FEM, Mr Cheng Chek Kweng in the assembly setup, Mr Paramasivam in sample preparations and Ms Ng Fern Lan in the SEM. This thesis is dedicated to my beloved wife, Gek Noi, for her unceasing love and devotion to me throughout my academic pursuit, and to my four lovely daughters, Jane, Sarah, Joann and Rayna, for constantly surrounding me with their joy and laughter.

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A challenge of 45 nm extreme low-k chip using Cu pillar bump as 1<sup>st</sup> interconnection

Cited by 8 publications

References 6 publications

Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

Reliability assessment of thermally compression bonded copper pillar on organic and ceramic substrates

Development of a flip-chip composite interconnection system

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