A circuit level fault model for resistive bridges

Abstract

Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test

“…The extra delay due to the resistive bridge defect is computed using the mathematical model proposed in [24]. Eq.…”

“…The parameters c, h and g are calculated according to the input pattern [24]. Since R br is connected to V DD and R n is the pull down network resistance, these parameters are given by, R n is computed as the ratio of the drain-source voltage and the drain current in the linear region.…”

Resistive Bridging Fault Simulation of Industrial Circuits

“…Simple bridging fault models ignore the resistance of the defect [3,[18][19][20][21][22][23]. Resistive bridging faults (RBF) are modeling this aspect with a higher degree of accuracy [ 16,[24][25][26][27][28][29][30][31][32][33][34][35]. Short defect resistance R,h is a random parameter not known in advance.…”

Delay fault modelling/simulation using VHDL-AMS in multi-Vdd systems

“…Fault simulations at circuit level will give more detailed results than gate level simulations [7]. Detailed power consumption and delays are some of the information that can be easily obtained from circuit level simualtions.…”