A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

Kawahara, Takayuki; Kawajiri, Y.; Kitsukawa, G.; Nakagome, Y.; Sagara, Kaoru; Kawamoto, Y.; Akiba, T.; Kato, S.; Kawase, Yuji; Itoh, K.

doi:10.1109/4.98968

Cited by 20 publications

(5 citation statements)

References 14 publications

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“…Regarding the slow speed issue, it is difficult for the PMOS latch to quickly charge up a highly capacitive data-line, resulting in slow sensing and restoring. Simple and practical ways to cope with the issue are to use an overdrive of common source (SP) at a higher voltage V OD than V DD [5], and to reduce the V T of the PMOS. The former, however, increases power dissipation due to raised supply V OD at every sense and write operations, while the latter increases leakage, which is intolerable for stand-alone applications although tolerable for embedded applications.…”

Section: A Proposal Of Asamentioning

confidence: 99%

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

Kotabe

Yanagawa

Takemura

et al. 2010

2010 IEEE Asian Solid-State Circuits Conference

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DL /DL SN SP M9 M10 V DD SGP Low-V T PMOS preamplifier CMOS SA M5 M7 SG Low-V T NMOS preamplifier M1 M2 M6 M8 DL /DL SP M5 SG M3 M4 M1 M2 M6 (a) (b) M11 M12 M3 M4 Figure 1. Schematic diagram: (a) previously proposed SA (SACP) and (b) proposed asymmetric cross-coupled SA (ASA). Abstract-A new sense amplifier (SA) and relevant circuits were proposed for low-power, high-speed, and small-sized 0.5-V gigabit DRAM arrays. The SA, consisting of a low-V T NMOS preamplifier and a cross-coupled high-V T PMOS latch, achieved 46% area reduction compared to our previously proposed SA with a low-V T CMOS preamplifier. Separation of the SA and a data-line pair, and overdrive of the latch achieved a restoring time of 13.4 ns and a sensing time of 6 ns. An adaptive leakage control of the preamplifier reduced the leakage current of the SA to 2% of that without the control.

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Section: A Proposal Of Asamentioning

confidence: 99%

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

Kotabe

Yanagawa

Takemura

et al. 2010

2010 IEEE Asian Solid-State Circuits Conference

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“…Increasing the size of SA MOSFETs to reduce (V T ) and using redundancy and/or ECC to prevent SAs from acquiring an excessively large ␦V T are effective solutions that are similar to those associated with the V T -mismatch issue previously explained in the subsection on cell signal charge in Section 2. In overdrive sensing [73,74], this problem is solved by applying a higher voltage solely to SA inputs by isolating the data line from the SA or by capacitive coupling. Using additional capacitors may be acceptable in e-DRAMs, where area is of less concern.…”

Section: Sense Amplifiersmentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

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“…In the overdrive sensing scheme [7,8,9] this problem is solved by applying a higher voltage solely to the SA-inputs with isolating the data line from SA or with capacitive coupling. The use of additional capacitors may be acceptable in eDRAMs for which area is not a concern.…”

Section: Memory Cells and Relevant Circuitsmentioning

confidence: 99%

Low-Voltage Embedded-RAM Technology: Present and Future

Itoh

Mizuno

2002

IFIP Advances in Information and Communication Technology

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Abstract:First, key issues for low-voltage «IV) embedded RAMs are summarized in terms of stable operation, suppression of leakage (gate-tunneling/subthreshold) currents, and speed variation of memory cells and peripheral logic circuits. Next, DRAM and SRAM cells to cope with the above issues, the circuit design focusing on subthreshold-current issue, and suppression of or compensation for design-parameter variations to reduce the speed variations are discussed. Voltage converters and power management for low-power and low-voltage operation are also explained. Finally, based on the above discussions, a perspective is given with emphasis on needs for simple/high signal-to-noise ratio memory cells (such as gain cells) with a pure logic compatible process, high-speed subthreshold-current reduction focusing on active mode, and memory-rich SoC architectures.

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A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

Cited by 20 publications

References 14 publications

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

Review and future prospects of low-voltage RAM circuits

Low-Voltage Embedded-RAM Technology: Present and Future

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