A Comparator-Based Rail Clamp

Venkatasubramanian, Ramachandran; Oertle, Kent; Ozev, Sule

doi:10.1109/tvlsi.2015.2446460

Cited by 5 publications

(3 citation statements)

References 13 publications

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“…(1)(2)(3)(4) As part of the whole-chip ESD protection, the power clamp circuit is indispensable to prevent thermal breakdown in the internal circuit of ICs. (5)(6)(7)(8)(9)(10)(11) It provides a lowimpedance path for each IC to discharge ESD energy from the power supply line (VDD) to the ground line (GND). A silicon controlled rectifier (SCR) can be used to construct a power clamp circuit; it has high robustness among the several widely used ESD protection devices since its parasitic cross-coupled bipolar junction transistors (BJTs) operate in positive feedback mode.…”

Section: Introductionmentioning

confidence: 99%

Modulation of Gate Work Function of Devices for Protection Against Electrostatic Discharge

Wu¹,

Wu²,

Yang³

et al. 2023

Sensors and Materials

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Electrostatic discharge (ESD) events are causing an increasing amount of damage in advanced integrated circuits (ICs). Among the onchip ESD protection devices, the silicon controlled rectifier (SCR) is the most robust. We have proposed a new SCR with an embedded n-type metal-oxide-semiconductor field-effect transistor (nMOSFET). By properly adjusting the gate work function of the nMOSFET, the SCR obtains a low trigger voltage of 1.5 V and a low leakage current of 7.6 × 10 −10 A. The overshoot voltage under a fast ESD event is also reduced owing to the strong conduction of the nMOSFET. By numerical simulation, we evaluate the impact of the temperature, noise, and stress waveform on the ESD performance. The results are discussed and detailed physical insights are given.

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Section: Introductionmentioning

confidence: 99%

Modulation of Gate Work Function of Devices for Protection Against Electrostatic Discharge

Wu¹,

Wu²,

Yang³

et al. 2023

Sensors and Materials

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show abstract

“…The circuitry consists of a pair of high-side and low-side diodes that direct the ESD current from input/ output (IO) pins to power supply (VDD) and ground rail (GND). The ESD discharging path between VDD and GND, formed by the primary ESD cell, is shared by two or more IO pins [22,23,24]. When multiple IO pins share one primary ESD cell, total chip area consumed by ESD circuits is reduced.…”

Section: Introductionmentioning

confidence: 99%

Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Lai

Wang

et al. 2019

IEICE Electron. Express

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In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based ESD protection circuits was investigated. The device simulation results show that the triggering voltage of the parasitic PNP varies with the geometry of the base region (e.g., the spacing between P+ and N-well). Furthermore, the test structures of parasitic PNP devices with different width of collector and base region were fabricated using the 65 nm low-k logic/Mixed-Mode CMOS process and characterized with the transmission line pulse (TLP) system. Both simulation and experimental results demonstrated that the triggering voltage of parasitic PNP structures has strong dependence on the base region and the simulation results also show that the triggering voltage is significantly affected by the spacing between P-well and N-well.

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“…Such a latched-on state can be catastrophic since the power and ground rails remain shorted till the power is reset. Moreover, many of these circuits are difficult to design into products because of the large process variation in today's processes [Venkatasubramanian et al 2015]. Because of these difficulties with other rail clamp circuits, the RC and single-inverter-based circuit continues to be widely used in the industry today.…”

Section: Introductionmentioning

confidence: 99%

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

Venkatasubramanian

Elio

Ozev

2016

ACM Trans. Des. Autom. Electron. Syst.

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RC and single-inverter-based rail clamps are widely used in semiconductor products for electrostatic discharge (ESD) protection. We propose a technology-node-independent design methodology for these rail clamp circuits that takes process, voltage, and temperature variations into consideration. The methodology can be used as a cookbook by the designer or be used to automate the entire design process. Tradeoffs between various design metrics such as ESD performance (Human Body Model), leakage, and area are considered. Simplified circuit models for the rail clamp are presented to gain insights into its working and to size the circuit components. A rail clamp for core power domain is designed using the proposed approach in 40nm low-power process and performance results of the design are also presented. The effectiveness of the design methodology is proven in three different technology nodes by comparing the obtained design with the best design from among 250,000 designs obtained by randomly sampling from the design space. ACM Reference Format:Ramachandran Venkatasubramanian, Robert Elio, and Sule Ozev. 2016. Process independent design methodology for the active RC and single-inverter-based rail clamp.

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A Comparator-Based Rail Clamp

Cited by 5 publications

References 13 publications

Modulation of Gate Work Function of Devices for Protection Against Electrostatic Discharge

Modulation of Gate Work Function of Devices for Protection Against Electrostatic Discharge

Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp

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