A computation and energy reduction technique for HEVC intra prediction

An efficient FPGA implementation of HEVC intra prediction

“…Data reuse technique is first used for reducing amount of computations performed by HEVC intra prediction algorithm in [8]. The same technique is also used in this paper.…”

“…A computation and energy reduction technique for HEVC intra prediction is proposed in [8]. This technique reorganizes the HEVC intra prediction equations by utilizing the fact that the sum of the coefficients used in each HEVC angular intra prediction equation is 32.…”

“…It, in the worst case, can process 55 Full HD (1920x1080) video frames per second. The proposed FPGA implementation has up to 15.97% less energy consumption than the FPGA implementation of HEVC intra prediction using the computation and energy reduction technique proposed in [8] and adders and shifters. The proposed FPGA implementation has up to 34.66% less energy consumption than the FPGA implementation of HEVC intra prediction using original prediction equations and DSP blocks.…”

“…Several HEVC intra prediction hardware are proposed in the literature [8]- [13]. In section III, they are compared with the HEVC intra prediction hardware proposed in this paper.…”

“…In Section II, HEVC intra prediction algorithm and the computation and energy reduction technique proposed in [8] are explained. The proposed HEVC intra prediction hardware is explained and the implementation results are given in Section III.…”