A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors

Ou, Jingzhao; Prasanna, Viktor K.

doi:10.1109/tvlsi.2007.912111

Cited by 4 publications

(3 citation statements)

References 17 publications

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“…These resources are complex and varied, with different levels of abstraction, including processing elements, specific process tasks, communication infrastructure, and others. Properly managing these resources involves controlling various actions like task mapping, scheduling, migration, element mapping, data distribution, and memory access [15,16].…”

Section: System Managementmentioning

confidence: 99%

A Survey of MPSoC Management toward Self-Awareness

Gonzalez-Martinez,

Sandoval-Arechiga,

Solis-Sanchez

et al. 2024

Micromachines

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Managing Multi-Processor Systems-on-Chip (MPSoCs) is becoming increasingly complex as demands for advanced capabilities rise. This complexity is due to the involvement of more processing elements and resources, leading to a higher degree of heterogeneity throughout the system. Over time, management schemes have evolved from simple to autonomous systems with continuous control and monitoring of various parameters such as power distribution, thermal events, fault tolerance, and system security. Autonomous management integrates self-awareness into the system, making it aware of its environment, behavior, and objectives. Self-Aware Cyber-Physical Systems-on-Chip (SA-CPSoCs) have emerged as a concept to achieve highly autonomous management. Communication infrastructure is also vital to SoCs, and Software-Defined Networks-on-Chip (SDNoCs) can serve as a base structure for self-aware systems-on-chip. This paper presents a survey of the evolution of MPSoC management over the last two decades, categorizing research works according to their objectives and improvements. It also discusses the characteristics and properties of SA-CPSoCs and explains why SDNoCs are crucial for these systems.

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Section: System Managementmentioning

confidence: 99%

A Survey of MPSoC Management toward Self-Awareness

Gonzalez-Martinez,

Sandoval-Arechiga,

Solis-Sanchez

et al. 2024

Micromachines

View full text Add to dashboard Cite

show abstract

“…Finally, Ou and Prasanna [2008] have demonstrated dedicated power management hardware peripherals tightly coupled to a single soft processor which runs a real-time operating system. They examine the power efficiency of the proposed scheme when selectively waking up the soft processor and its hardware components, and put them into proper activation states based on the hardware resource requirements of the tasks under execution.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs

Kornaros

Pnevmatikatos

2014

ACM Trans. Reconfigurable Technol. Syst.

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Advances in silicon process technology have made it possible to include multiple processor cores on a single die. Billion transistor architectures usually in the form of networks-on-chip present a wide range of challenges in design, microarchitecture, and algorithmic levels with significant impact to system performance and power consumption. In this article, we propose efficient methods and mechanisms that exploit a heterogeneous network-on-chip (NoC) to achieve a power-and thermal-aware coherent system. To this end, we utilize different management techniques which employ dynamic frequency scaling circuitry and power and temperature sensors per node to achieve real-time workload prediction and allocation at node and system level by low-cost threads. The developed heterogeneous multicoprocessing infrastructure is utilized to evaluate diverse policies for power-aware computing in terms of effectiveness and in relation to distributed sensor-conscious management. The proposed reconfigurable architecture supports coprocessor accelerators per node, monitors the program's power profile on-the-fly, and balances power and thermal behavior at the NoC level. Overall, these techniques form a system exploration methodology using a multi-FPGA emulation platform showing a minimum complexity overhead.

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“…According to the commands, operating system to establish a number of tasks and scheduling. If there are enough hardware resources to complete the task, operating system provides acquisition pulse to A/D converter, and controls the acquisition time and frequency; configure FPGAs according need [9].…”

Section: Advanced Materials Research Vols 546-547mentioning

confidence: 99%

Design of FPGA-Based Fault-Tolerant Embedded System

Xiong

Wang

Zeng

2012

AMR

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Fault tolerant is one of major requirements for embedded systems. As the embedded systems become more and more complex, more chances for various fault. When design embedded system developer has to handle these faults. Before handling faults designer has to identify and understand the types and nature of faults.Faults is the sources for low dependability, faults can be hardware and software. Hardware faults can be distinguished from systematic faults like software or design errors. The Fault can be deleted, such as extensive testing or formal verification and tolerated by fault tolerance techniques. We restrict ourselves to the problem of fault tolerance and refer to other methods for troubleshooting.This paper discusses a new design method about the fault tolerant system of embedded system. We designed a fault tolerant system of data acquisition system in dynamically re-configurable FPGA. The experiment results show that the system not only be able to higher self-adaptive ability and reliability, but also can Through the FGPA to complete a specific algorithm.

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A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors

Cited by 4 publications

References 17 publications

A Survey of MPSoC Management toward Self-Awareness

A Survey of MPSoC Management toward Self-Awareness

Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs

Design of FPGA-Based Fault-Tolerant Embedded System

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