A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Verma, Deeksha; Shehzad, Khuram; Khan, Danial; Kim, Sung Jin; Pu, Young Gun; Yoo, Sang-Sun; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon

doi:10.3390/electronics9071100

Cited by 17 publications

(13 citation statements)

References 25 publications

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“…The ADC achieved an SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in FoMs of 8.69 and 11.8 fJ/conversion step, respectively. The FOM [40] is shown as Equation (17):…”

Section: Discussionmentioning

confidence: 99%

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2.

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Section: Discussionmentioning

confidence: 99%

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Zheng

Ren

2022

Electronics

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“…Nowadays, for linear sampling, a bootstrap switch is frequently used, and its non-idealities have become pronounced; thus, its linearity is seriously degrading. Several techniques have been used to improve the performance of the bootstrap switch, such as modifying the circuit network or incorporating fast-turn-on circuits [ 13 ]. In Figure 2 , we propose a technique to improve the linearity of the bootstrap switch.…”

Section: Circuit Implementationmentioning

confidence: 99%

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

Verma

Shehzad

Kim

et al. 2022

Sensors

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A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

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“…The Area and power consumption of the capacitive DAC are significantly large for the high-resolution ADC such as over 10-bit resolution. To lower the capacitance from the DAC part, we adopt the common-mode charge recovery (CMCR) switching method [ 26 ]. With this switching, we use the possible minimum size of the unit capacitor in a capacitive DAC layout.…”

Section: Circuit Implementationmentioning

confidence: 99%

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Shehzad

Verma

Khan

et al. 2021

Sensors

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A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Cited by 17 publications

References 25 publications

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

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