A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level

Segura, J.; Benito, Carol de; Rubio, Antonio; Hawkins, C.F.

doi:10.1109/test.1995.529882

Cited by 37 publications

(14 citation statements)

References 7 publications

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“…Moreover, GOS causes a weak inversion and tightens the channel for carriers, leads to a slight increase of V T h (ΔV T h = 170mV ). The negative ID when the VDD = low, which happens in bulk CMOS and FinFET [25,16] , is observed here when the remaining gates of the transistor allow carriers to pass through the channel. For example, for faulty n-type devices used in SP logic gates, polarity controls constantly permit electrons to pass through channel, and therefore negative ID exists when the VD decreases.…”

Section: B Tig-sinwfet Performance In Presence Of Gosmentioning

confidence: 72%

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Mohammadi¹,

Gaillardon²,

Micheli³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals.

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Section: B Tig-sinwfet Performance In Presence Of Gosmentioning

confidence: 72%

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Mohammadi¹,

Gaillardon²,

Micheli³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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“…For example, MTTF 14 is the MTTF of the 4 th transistor in respect to TDDB (with TDDB being the first failure mechanism).…”

Section: Fundamentals Of Reliabilitymentioning

confidence: 99%

“…Secondly, we simulated various benchmark circuits based on the previously characterized logic gates and investigated the impact of shadow transistors on the critical design parameters. For the simulations of the different mechanisms of gate oxide breakdown, we chose equivalent circuits that can be used in standard CAD environments [14]. Figure 2 a) depicts for instance the electrical defect model of gate-channel breakdown.…”

Section: Setupmentioning

confidence: 99%

Encountering gate oxide breakdown with shadow transistors to increase reliability

Cornelius

Sill

Sämrow

et al. 2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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Device scaling has enabled continuous performance increase of integrated circuits. However, severe reliability and yield concerns are arising against the background of nanotechnology. Traditionally, most causes and countermeasures were solely considered manufacturing issues, but lately, we have seen a shift towards operational reliability issues. Though, besides intense research on soft-errors and system-level approaches very little effort is put into low-level design solutions in order to enhance lifetime reliability. Hence, we demonstrate that redundant transistor insertion does improve system reliability significantly as regards Time-Dependent Dielectric Breakdown (TDDB). Furthermore, we introduce an algorithm which identifies the transistors being most vulnerable to TDDB. Subsequently, redundant transistors (called shadow transistors) are inserted at the previously identified instances. Lastly, we argue for applying high threshold voltage devices for the redundant transistors. Finally, we present results for a set of benchmark circuits and prove the combined approach successful. The enhanced designs were on average 41.8 % more reliable compared to the initial designs in respect of TDDB at the price of moderately increased power consumption and delay.

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“…However, when the dielectric thickness of FinFETs is scaled to 1∼5nm [10] [11], and the nonconformal deposition of the dielectric layer is reported [12], the FinFET with Fin-LER suffers the poor insulator coverage at the sidewalls as shown in Figure 1(c). The gate oxide short defects may consequently occur [13] [14].…”

Section: Introductionmentioning

confidence: 99%

Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs

Lin

Chao

Hsu

2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods. 2013 IEEE 31st VLSI Test Symposium (VTS) 978-1-4673-5543-8/13/$31.00 ©2013 IEEE

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A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level

Cited by 37 publications

References 7 publications

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Encountering gate oxide breakdown with shadow transistors to increase reliability

Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs

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