A differential-capacitance read scheme for FeRAMs

Abstract

A differential-capacitance read scheme keeps the plateline voltage constant at ground and begins sensing the stored data immediately after a wordline is raised, hence eliminating the time spent in conventional read schemes in raising the highly capacitive plateline and in charge sharing of the bitlines with the ferroelectric capacitors. The proposed read scheme is used in a 256x128-bit testchip that features both 2T-2C and IT-1C cells in 0.35pm technology. The read scheme achieves a 40% reduction in access time.

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)

“…DCRS, on the other hand, compares the capacitance of the cell capacitor against a reference capacitance and starts the detection process right after a memory row is selected, eliminating the charge transfer and charge sharing times to achieve a smaller read access time. We have shown previously by simulation results [4] that DCRS can achieve 20% to 40% smaller read access time compared to the other three read schemes. In this paper, we present two circuit implementations of DCRS along with a comparative study of their complexity, area overhead, and sensitivity to the mismatches.…”

“…15(b) and Fig. 15(c), introduced in [4], and an oversized reference capacitor [1]. In order to compare each cell capacitor with different reference capacitor sizes, four different reference capacitor sizes, 1X to 4X, are used in the test chip.…”

“…2, to detect the data stored in a cell. The differential capacitance read scheme (DCRS) [4], however, utilizes the capacitance difference of the ferroelectric capacitor in states "1" and "0"…”

“…Fig. 3(a) presents the basic concept of DCRS [4]. We describe the operation of this circuit during the read cycle using the equivalent circuit shown in Fig.…”