Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)

A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed, in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier. Compared with the conventional symmetrical scheme in Ref. [8], the proposed scheme increases the sense margin of the readout current by 53.9% and decreases the sensing power consumption by 14.1%, at the cost of an additional 7.89% area of the sensing scheme. An experimental FRAM prototype utilizing the proposed asymmetrical scheme is implemented in a 0.35 m three metal process, in which the function of the prototype is verified.

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“…How large the sense margin could be depends on three important coefficients, ˛, ˇand , which are defined in Eqs. ( 1)- (3).…”

Section: Discussion and Comparisonmentioning

confidence: 99%

An asymmetrical sensing scheme for 1T1C FRAM to increase the sense margin

Jia¹,

Zhongren²,

Tianling³

et al. 2010

J. Semicond.

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“…Among the nonvolatile memories, FeRAM is a better choice, because of its short write access time and low power and voltage write operation [13], which results in fast instantiation of the algorithm with minimum power. Differential capacitance read scheme (DCRS) [27] can be used for the FeRAM read operation to achieve short access time (less than 50 ns) that satisfies the available time budget for smart card applications ( ns approximately, which corresponds to MHz). The main disadvantage of FeRAM over other nonvolatile memories is its higher power consumption for read operation.…”

Section: A Architecturementioning

confidence: 99%

An area-efficient universal cryptography processor for smart cards

Eslami

Sheikholeslami

Gulak

et al. 2006

IEEE Trans. VLSI Syst.

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Abstract-Cryptography circuits for smart cards and portable electronic devices provide user authentication and secure data communication. These circuits should, in general, occupy small chip area, consume low power, handle several cryptography algorithms, and provide acceptable performance. This paper presents, for the first time, a hardware implementation of three standard cryptography algorithms on a universal architecture. The microcoded cryptography processor targets smart card applications and implements both private key and public key algorithms and meets the power and performance specifications and is as small as 2.25 mm 2 in 0.18-m 6LM CMOS. A new algorithm is implemented by changing the contents of the memory blocks that are implemented in ferroelectric RAM (FeRAM). Using FeRAM allows nonvolatile storage of the configuration bits, which are changed only when a new algorithm instantiation is required.

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